Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <types.h> |
| 18 | #include <arch/io.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 19 | #include <halt.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 20 | #include "gm45.h" |
| 21 | |
| 22 | void gm45_early_reset(void/*const timings_t *const timings*/) |
| 23 | { |
| 24 | int ch, r; |
| 25 | |
| 26 | /* Reset DRAM power-up settings in CLKCFG (they are not |
| 27 | affected by system reset but may disrupt raminit). */ |
| 28 | MCHBAR32(CLKCFG_MCHBAR) = |
| 29 | (MCHBAR32(CLKCFG_MCHBAR) & ~(3 << 21)) | (1 << 3); |
| 30 | |
| 31 | /*\ Next settings are the real purpose of this function: |
| 32 | If these steps are not performed, reset results in power off. \*/ |
| 33 | |
| 34 | /* Initialize some DRAM settings to 1 populated rank of 128MB. */ |
| 35 | FOR_EACH_CHANNEL(ch) { |
| 36 | /* Configure DRAM control mode. */ |
| 37 | MCHBAR32(CxDRC0_MCHBAR(ch)) = |
| 38 | (MCHBAR32(CxDRC0_MCHBAR(ch)) & ~CxDRC0_RANKEN_MASK) | |
| 39 | (ch ? 0 : CxDRC0_RANKEN(0)); |
| 40 | MCHBAR32(CxDRC1_MCHBAR(ch)) = |
| 41 | (MCHBAR32(CxDRC1_MCHBAR(ch)) | CxDRC1_NOTPOP_MASK) & |
| 42 | ~(ch ? 0 : CxDRC1_NOTPOP(0)); |
| 43 | MCHBAR32(CxDRC2_MCHBAR(ch)) = |
| 44 | (MCHBAR32(CxDRC2_MCHBAR(ch)) | CxDRC2_NOTPOP_MASK) & |
| 45 | ~(ch ? 0 : CxDRC2_NOTPOP(0)); |
| 46 | /*if (timings && (timings->mem_clock == MEM_CLOCK_1067MT)) |
| 47 | MCHBAR32(CxDRC2_MCHBAR(ch)) |= CxDRC2_CLK1067MT;*/ |
| 48 | |
| 49 | /* Program rank boundaries (CxDRBy). */ |
| 50 | for (r = 0; r < RANKS_PER_CHANNEL; r += 2) |
| 51 | MCHBAR32(CxDRBy_MCHBAR(ch, r)) = |
| 52 | CxDRBy_BOUND_MB(r, 128) | |
| 53 | CxDRBy_BOUND_MB(r+1, 128); |
| 54 | } |
| 55 | /* Set DCC mode to no operation and do magic 0xf0 thing. */ |
| 56 | MCHBAR32(DCC_MCHBAR) = |
| 57 | (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; |
| 58 | u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 59 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); |
| 60 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 61 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); |
| 62 | /* Normally, we would set this after successful raminit. */ |
| 63 | MCHBAR32(DCC_MCHBAR) |= (1 << 19); |
| 64 | |
| 65 | /* Perform system reset through CF9 interface. */ |
| 66 | outb(0x02, 0xcf9); /* Set system reset bit. */ |
| 67 | outb(0x06, 0xcf9); /* Set cpu reset bit, too. */ |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 68 | halt(); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 69 | } |