Martin Roth | bf6b83a | 2015-10-11 10:37:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Martin Roth | bf6b83a | 2015-10-11 10:37:02 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <stdlib.h> |
| 19 | #include <console/console.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <device/pci_def.h> |
| 22 | #include <elog.h> |
| 23 | #include "northbridge.h" |
| 24 | |
| 25 | static void sandybridge_setup_bars(void) |
| 26 | { |
| 27 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 28 | /* Set up all hardcoded northbridge BARs */ |
| 29 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
| 30 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); |
| 31 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); |
| 32 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32); |
| 33 | pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ |
| 34 | pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32); |
| 35 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); |
| 36 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); |
| 37 | |
| 38 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 39 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); |
| 40 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |
| 41 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); |
| 42 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); |
| 43 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); |
| 44 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); |
| 45 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); |
| 46 | |
| 47 | #if CONFIG_ELOG_BOOT_COUNT |
| 48 | /* Increment Boot Counter for non-S3 resume */ |
| 49 | if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && |
| 50 | ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) |
| 51 | boot_count_increment(); |
| 52 | #endif |
| 53 | |
| 54 | printk(BIOS_DEBUG, " done.\n"); |
| 55 | |
| 56 | #if CONFIG_ELOG_BOOT_COUNT |
| 57 | /* Increment Boot Counter except when resuming from S3 */ |
| 58 | if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && |
| 59 | ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) |
| 60 | return; |
| 61 | boot_count_increment(); |
| 62 | #endif |
| 63 | } |
| 64 | |
| 65 | void sandybridge_early_initialization(int chipset_type) |
| 66 | { |
| 67 | u32 capid0_a; |
| 68 | u8 reg8; |
| 69 | |
| 70 | /* Device ID Override Enable should be done very early */ |
| 71 | capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); |
| 72 | if (capid0_a & (1 << 10)) { |
| 73 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); |
| 74 | reg8 &= ~7; /* Clear 2:0 */ |
| 75 | |
| 76 | if (chipset_type == SANDYBRIDGE_MOBILE) |
| 77 | reg8 |= 1; /* Set bit 0 */ |
| 78 | |
| 79 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); |
| 80 | } |
| 81 | |
| 82 | /* Setup all BARs required for early PCIe and raminit */ |
| 83 | sandybridge_setup_bars(); |
| 84 | } |