| Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009-2010 iWave Systems |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef __PRE_RAM__ |
| 18 | #define __PRE_RAM__ // Use simple device model for this file even in ramstage |
| 19 | #endif |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <device/pci_def.h> |
| 24 | #include <device/pnp_def.h> |
| 25 | #include <cpu/x86/lapic.h> |
| 26 | #include "northbridge.h" |
| 27 | |
| 28 | /* |
| 29 | * Restricted Access Regions: |
| 30 | * |
| 31 | * MCR - Message Control Register |
| 32 | * 31 24 16 8 4 0 |
| 33 | * ---------------------------------------------------------------------------- |
| 34 | * | | | Target | Write | | |
| 35 | * | Opcode | Port | register | byte | Reserved | |
| 36 | * | | | Address | Enables | | |
| 37 | * ---------------------------------------------------------------------------- |
| 38 | * |
| 39 | * MDR - Message Data Register |
| 40 | * 31 0 |
| 41 | * ---------------------------------------------------------------------------- |
| 42 | * | | |
| 43 | * | Data | |
| 44 | * | | |
| 45 | * ---------------------------------------------------------------------------- |
| 46 | */ |
| 47 | |
| 48 | #define MSG_OPCODE_READ 0x10 << 24 |
| 49 | #define MSG_OPCODE_WRITE 0x11 << 24 |
| 50 | |
| 51 | #define MCR 0xD0 |
| 52 | #define MDR 0xD4 |
| 53 | #define MCRE 0xD8 |
| 54 | |
| 55 | u32 sideband_read(int port, int reg) |
| 56 | { |
| 57 | pci_write_config32(PCI_DEV(0, 0, 0), MCR, |
| 58 | (MSG_OPCODE_READ | (port << 16) | (reg << 8))); |
| 59 | return pci_read_config32(PCI_DEV(0, 0, 0), MDR); |
| 60 | } |
| 61 | |
| 62 | void sideband_write(int port, int reg, long data) |
| 63 | { |
| 64 | pci_write_config32(PCI_DEV(0, 0, 0), MDR, data); |
| 65 | pci_write_config32(PCI_DEV(0, 0, 0), MCR, |
| 66 | (MSG_OPCODE_WRITE | (port << 16) | (reg << 8) | (0xF << 4))); |
| 67 | pci_read_config32(PCI_DEV(0, 0, 0), MDR); |
| 68 | } |