Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <arch/acpi.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <stdint.h> |
| 22 | #include <delay.h> |
| 23 | #include <cpu/intel/fsp_model_406dx/model_406dx.h> |
| 24 | #include <cpu/x86/msr.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <device/pci_ids.h> |
| 28 | #include <stdlib.h> |
| 29 | #include <string.h> |
| 30 | #include <cpu/cpu.h> |
| 31 | #include <cbmem.h> |
| 32 | #include "chip.h" |
| 33 | #include "northbridge.h" |
| 34 | #include <drivers/intel/fsp1_0/fsp_util.h> |
| 35 | #include <cpu/x86/lapic.h> |
| 36 | |
| 37 | static int bridge_revision_id = -1; |
| 38 | |
| 39 | int bridge_silicon_revision(void) |
| 40 | { |
| 41 | if (bridge_revision_id < 0) { |
| 42 | uint8_t stepping = cpuid_eax(1) & 0xf; |
| 43 | uint8_t bridge_id = pci_read_config16( |
| 44 | dev_find_slot(0, PCI_DEVFN(0, 0)), |
| 45 | PCI_DEVICE_ID) & 0xf0; |
| 46 | bridge_revision_id = bridge_id | stepping; |
| 47 | } |
| 48 | return bridge_revision_id; |
| 49 | } |
| 50 | |
| 51 | /* Reserve everything between A segment and 1MB: |
| 52 | * |
| 53 | * 0xa0000 - 0xbffff: legacy VGA |
| 54 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 55 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
| 56 | */ |
| 57 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
| 58 | static const int legacy_hole_size_k = 384; |
| 59 | |
| 60 | static int get_pcie_bar(u32 *base, u32 *len) |
| 61 | { |
| 62 | device_t dev; |
| 63 | u32 pciexbar_reg; |
| 64 | |
| 65 | *base = 0; |
| 66 | *len = 0; |
| 67 | |
| 68 | dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 69 | if (!dev) |
| 70 | return 0; |
| 71 | |
| 72 | pciexbar_reg = sideband_read(B_UNIT, BECREG); |
| 73 | |
| 74 | if (!(pciexbar_reg & (1 << 0))) |
| 75 | return 0; |
| 76 | |
| 77 | *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | |
| 78 | (1 << 28)); |
| 79 | *len = 256 * 1024 * 1024; /* 256MB ECAM range */ |
| 80 | return 1; |
| 81 | |
| 82 | } |
| 83 | |
| 84 | static int add_fixed_resources(struct device *dev, int index) |
| 85 | { |
| 86 | struct resource *resource; |
| 87 | u32 pcie_config_base, pcie_config_size; |
| 88 | |
| 89 | |
| 90 | if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { |
| 91 | printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " |
| 92 | "size=0x%x\n", pcie_config_base, pcie_config_size); |
| 93 | resource = new_resource(dev, index++); |
| 94 | resource->base = (resource_t) pcie_config_base; |
| 95 | resource->size = (resource_t) pcie_config_size; |
| 96 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 97 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 98 | } |
| 99 | |
| 100 | resource = new_resource(dev, index++); /* Local APIC */ |
| 101 | resource->base = LAPIC_DEFAULT_BASE; |
| 102 | resource->size = 0x00001000; |
| 103 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 104 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 105 | |
| 106 | mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); |
| 107 | |
| 108 | return index; |
| 109 | } |
| 110 | |
| 111 | static void mc_add_dram_resources(device_t dev) |
| 112 | { |
| 113 | u32 tomlow, bmbound, bsmmrrl, bsmmrrh; |
| 114 | u64 bmbound_hi; |
| 115 | int index = 0; |
| 116 | |
| 117 | /* |
| 118 | * These are the host memory ranges : |
| 119 | * - 0 -> SMM (SMMRRL) : cacheable |
| 120 | * - SMM -> LOW TOM (BMBOUND) : cacheable WP |
| 121 | * - 4GB -> HIGH TOM (BMBOUND_HI): cacheable |
| 122 | * |
| 123 | */ |
| 124 | |
| 125 | tomlow = bmbound = sideband_read(B_UNIT, BMBOUND); |
| 126 | printk(BIOS_SPEW, "Top of Low Used DRAM (BMBOUND): 0x%08x\n", bmbound); |
| 127 | |
| 128 | bmbound_hi = (u64)(sideband_read(B_UNIT, BMBOUND_HI)) << 4; |
| 129 | printk(BIOS_SPEW, "Top of Upper Used DRAM (BMBOUND_HI): 0x%llx\n", bmbound_hi); |
| 130 | |
| 131 | bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; |
| 132 | bsmmrrh = ((sideband_read(B_UNIT, BSMMRRH) + 1) << 20) - 1; |
| 133 | if (bsmmrrl) { |
| 134 | tomlow = bsmmrrl; |
| 135 | printk(BIOS_DEBUG, "SMM memory location: 0x%x SMM memory size: 0x%x\n", bsmmrrl, (bsmmrrh - bsmmrrl + 1)); |
| 136 | printk(BIOS_DEBUG, "Subtracting %dM for SMM\n", (bmbound - bsmmrrl) >> 20); |
| 137 | } |
| 138 | tomlow -= FSP_RESERVE_MEMORY_SIZE; |
| 139 | printk(BIOS_SPEW, "Available memory below 4GB: 0x%08x (%dM)\n", tomlow, tomlow >> 20); |
| 140 | |
| 141 | /* Report the memory regions. */ |
| 142 | ram_resource(dev, index++, 0, legacy_hole_base_k); |
| 143 | ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, |
| 144 | ((tomlow >> 10) - (legacy_hole_base_k + legacy_hole_size_k))); |
| 145 | |
| 146 | mmio_resource(dev, index++, tomlow >> 10, (bmbound - bsmmrrl) >> 10); |
| 147 | |
| 148 | if (bmbound_hi > 0x100000000) { |
| 149 | ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10 ); |
| 150 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (bmbound_hi - 0x100000000) >> 20); |
| 151 | } |
| 152 | |
| 153 | index = add_fixed_resources(dev, index); |
| 154 | } |
| 155 | |
| 156 | static void mc_read_resources(device_t dev) |
| 157 | { |
| 158 | /* Call the normal read_resources */ |
| 159 | pci_dev_read_resources(dev); |
| 160 | |
| 161 | /* Calculate and add DRAM resources. */ |
| 162 | mc_add_dram_resources(dev); |
| 163 | } |
| 164 | |
| 165 | static void pci_domain_set_resources(device_t dev) |
| 166 | { |
| 167 | /* |
| 168 | * Assign memory resources for PCI devices |
| 169 | */ |
| 170 | mc_add_dram_resources(dev); |
| 171 | |
| 172 | assign_resources(dev->link_list); |
| 173 | } |
| 174 | |
| 175 | static void mc_set_resources(device_t dev) |
| 176 | { |
| 177 | /* Call the normal set_resources */ |
| 178 | pci_dev_set_resources(dev); |
| 179 | } |
| 180 | |
| 181 | static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 182 | { |
| 183 | if (!vendor || !device) { |
| 184 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 185 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 186 | } else { |
| 187 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 188 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 189 | } |
| 190 | } |
| 191 | |
| 192 | static void northbridge_init(struct device *dev) |
| 193 | { |
| 194 | } |
| 195 | |
| 196 | static void northbridge_enable(device_t dev) |
| 197 | { |
| 198 | } |
| 199 | |
| 200 | static struct pci_operations intel_pci_ops = { |
| 201 | .set_subsystem = intel_set_subsystem, |
| 202 | }; |
| 203 | |
| 204 | static struct device_operations pci_domain_ops = { |
| 205 | .read_resources = pci_domain_read_resources, |
| 206 | .set_resources = pci_domain_set_resources, |
| 207 | .enable_resources = NULL, |
| 208 | .init = NULL, |
| 209 | .scan_bus = pci_domain_scan_bus, |
| 210 | .ops_pci_bus = pci_bus_default_ops, |
| 211 | }; |
| 212 | |
| 213 | static struct device_operations mc_ops = { |
| 214 | .read_resources = mc_read_resources, |
| 215 | .set_resources = mc_set_resources, |
| 216 | .enable_resources = pci_dev_enable_resources, |
| 217 | .init = northbridge_init, |
| 218 | .acpi_fill_ssdt_generator = northbridge_acpi_fill_ssdt_generator, |
| 219 | .enable = northbridge_enable, |
| 220 | .scan_bus = 0, |
| 221 | .ops_pci = &intel_pci_ops, |
| 222 | }; |
| 223 | |
| 224 | /* |
| 225 | * The following entries are taken from Intel document number 510524, rev 1.6: |
| 226 | * Rangeley SoC External Design Specification (EDS) |
| 227 | * Section 10.3 PCI Configuration Space |
| 228 | * Table 10-6. PCI Devices and Functions |
| 229 | * |
| 230 | * These are the Device ID values for the item at bus 0, device 0, function 0. |
| 231 | */ |
| 232 | static const unsigned short pci_device_ids[] = { |
| 233 | 0x1f00, 0x1f01, 0x1f02, 0x1f03, |
| 234 | 0x1f04, 0x1f05, 0x1f06, 0x1f07, |
| 235 | 0x1f08, 0x1f09, 0x1f0a, 0x1f0b, |
| 236 | 0x1f0c, 0x1f0d, 0x1f0e, 0x1f0f, |
| 237 | 0, /* -- END OF LIST -- */ |
| 238 | }; |
| 239 | |
| 240 | static const struct pci_driver mc_driver __pci_driver = { |
| 241 | .ops = &mc_ops, |
| 242 | .vendor = PCI_VENDOR_ID_INTEL, |
| 243 | .devices = pci_device_ids, |
| 244 | }; |
| 245 | |
| 246 | static void cpu_bus_init(device_t dev) |
| 247 | { |
| 248 | initialize_cpus(dev->link_list); |
| 249 | } |
| 250 | |
| 251 | static struct device_operations cpu_bus_ops = { |
| 252 | .read_resources = DEVICE_NOOP, |
| 253 | .set_resources = DEVICE_NOOP, |
| 254 | .enable_resources = DEVICE_NOOP, |
| 255 | .init = cpu_bus_init, |
| 256 | .scan_bus = 0, |
| 257 | }; |
| 258 | |
| 259 | static void enable_dev(device_t dev) |
| 260 | { |
| 261 | /* Set the operations if it is a special bus type */ |
| 262 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 263 | dev->ops = &pci_domain_ops; |
| 264 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 265 | dev->ops = &cpu_bus_ops; |
| 266 | } |
| 267 | } |
| 268 | |
| 269 | struct chip_operations northbridge_intel_fsp_rangeley_ops = { |
| 270 | CHIP_NAME("Intel Rangeley Northbridge") |
| 271 | .enable_dev = enable_dev, |
| 272 | }; |