Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * Copyright (C) 2015 Intel Corporation |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef _FSP_RANGELEY_CHIP_H_ |
| 18 | #define _FSP_RANGELEY_CHIP_H_ |
| 19 | |
| 20 | #include <arch/acpi.h> |
| 21 | #include <drivers/intel/fsp1_0/fsp_values.h> |
| 22 | |
| 23 | struct northbridge_intel_fsp_rangeley_config { |
| 24 | |
| 25 | /* Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1) */ |
| 26 | /* Valid values: 0 - 15 */ |
| 27 | uint8_t MrcRmtCpgcExpLoopCntValue; |
| 28 | /* Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1) */ |
| 29 | /* Valid values: 0 - 15 */ |
| 30 | uint8_t MrcRmtCpgcNumBursts; |
| 31 | /* DIMM SPD SMBus Addresses */ |
| 32 | uint8_t SpdBaseAddress_0_0; |
| 33 | uint8_t SpdBaseAddress_0_1; |
| 34 | uint8_t SpdBaseAddress_1_0; |
| 35 | uint8_t SpdBaseAddress_1_1; |
| 36 | |
| 37 | uint8_t EnableLan; |
| 38 | uint8_t EnableSata2; |
| 39 | uint8_t EnableSata3; |
| 40 | uint8_t EnableIQAT; |
| 41 | uint8_t EnableUsb20; |
| 42 | uint8_t PrintDebugMessages; |
| 43 | uint8_t Fastboot; |
| 44 | uint8_t EccSupport; |
| 45 | uint8_t SpdWriteProtect; |
| 46 | /* Enable = Memory Down, Disable = DIMM */ |
| 47 | uint8_t MemoryDown; |
| 48 | /* Enable the Rank Margin Tool, needs PrintDebugMessages */ |
| 49 | uint8_t MrcRmtSupport; |
| 50 | |
| 51 | /* PCIe port bifurcation control */ |
| 52 | uint8_t Bifurcation; |
| 53 | #define BIFURCATION_4_4_4_4 0 |
| 54 | #define BIFURCATION_4_4_8 1 |
| 55 | #define BIFURCATION_8_4_4 2 |
| 56 | #define BIFURCATION_8_8 3 |
| 57 | #define BIFURCATION_16 4 |
| 58 | |
| 59 | /* PCIe port de-emphasis control */ |
| 60 | uint8_t PcdPcieRootPort1DeEmphasis; |
| 61 | uint8_t PcdPcieRootPort2DeEmphasis; |
| 62 | uint8_t PcdPcieRootPort3DeEmphasis; |
| 63 | uint8_t PcdPcieRootPort4DeEmphasis; |
| 64 | #define DE_EMPHASIS_DEFAULT 0 |
| 65 | #define DE_EMPHASIS_MINUS_6_0_DB 1 |
| 66 | #define DE_EMPHASIS_MINUS_3_5_DB 2 |
| 67 | }; |
| 68 | |
| 69 | #endif |