| Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2012 The Chromium OS Authors |
| 6 | * Copyright (C) 2013 Sage Electronic Engineering, LLC |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; version 2 of |
| 11 | * the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <types.h> |
| 20 | #include <string.h> |
| 21 | #include <console/console.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <arch/acpi.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <device/pci_ids.h> |
| 27 | #include <arch/acpi.h> |
| 28 | #include <arch/acpigen.h> |
| 29 | #include "northbridge.h" |
| 30 | |
| 31 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 32 | { |
| 33 | device_t dev; |
| 34 | u32 pciexbar = 0; |
| 35 | u32 pciexbar_reg; |
| 36 | int max_buses; |
| 37 | int pci_dev_id; |
| 38 | |
| 39 | for (pci_dev_id = PCI_DEVICE_ID_RG_MIN; pci_dev_id <= PCI_DEVICE_ID_RG_MAX; pci_dev_id++) { |
| 40 | dev = dev_find_device(PCI_VENDOR_ID_INTEL, pci_dev_id, 0); |
| 41 | if (dev) |
| 42 | break; |
| 43 | } |
| 44 | |
| 45 | if (!dev) |
| 46 | return current; |
| 47 | |
| 48 | pciexbar_reg = sideband_read(B_UNIT, BECREG); |
| 49 | |
| 50 | /* MMCFG not supported or not enabled. */ |
| 51 | if (!(pciexbar_reg & (1 << 0))) |
| 52 | return current; |
| 53 | |
| 54 | /* 256MB ECAM range */ |
| 55 | pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); |
| 56 | max_buses = 256; |
| 57 | |
| 58 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, |
| 59 | pciexbar, 0x0, 0x0, max_buses - 1); |
| 60 | |
| 61 | return current; |
| 62 | } |
| 63 | |
| 64 | void northbridge_acpi_fill_ssdt_generator(device_t device) |
| 65 | { |
| 66 | u32 bmbound; |
| 67 | char pscope[] = "\\_SB.PCI0"; |
| 68 | |
| 69 | bmbound = sideband_read(B_UNIT, BMBOUND); |
| 70 | acpigen_write_scope(pscope); |
| 71 | acpigen_write_name_dword("BMBD", bmbound); |
| 72 | acpigen_pop_len(); |
| 73 | generate_cpu_entries(device); |
| 74 | } |