Andrew Wu | 0651072 | 2013-06-21 21:37:05 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 DMP Electronics Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Andrew Wu | 0651072 | 2013-06-21 21:37:05 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | static u16 get_mask(u16 bit_width, u16 bit_offset) |
| 17 | { |
| 18 | u16 mask = (((1 << bit_width) - 1) << bit_offset); |
| 19 | return mask; |
| 20 | } |
| 21 | |
| 22 | static u16 set_bitfield(u16 val, u16 bits, u16 bit_width, u16 bit_offset) |
| 23 | { |
| 24 | u16 mask = get_mask(bit_width, bit_offset); |
| 25 | val = (val & ~mask) | (bits << bit_offset); |
| 26 | return val; |
| 27 | } |
| 28 | |
| 29 | static u16 get_bitfield(u16 val, u16 bit_width, u16 bit_offset) |
| 30 | { |
| 31 | u16 mask = get_mask(bit_width, bit_offset); |
| 32 | return (val & mask) >> bit_offset; |
| 33 | } |
| 34 | |
| 35 | static u8 check_address_bit(int addr_bit) |
| 36 | { |
| 37 | u16 dummy; |
| 38 | *(volatile u16 *)(0) = 0; |
| 39 | dummy = *(volatile u16 *)(0); // read push write |
| 40 | *(volatile u16 *)(1 << addr_bit) = 0x5a5a; |
| 41 | dummy = *(volatile u16 *)(1 << addr_bit); // read push write |
| 42 | if ((*(volatile u16 *)(0)) != 0) |
| 43 | return 0; // address bit wrapped. |
| 44 | return 1; // address bit not wrapped. |
| 45 | } |
| 46 | |
| 47 | static u8 check_dram_side(int addr_bit) |
| 48 | { |
| 49 | *(volatile u16 *)(1 << addr_bit) = 0x5a5a; |
| 50 | *(volatile u16 *)(0) = 0; |
| 51 | if ((*(volatile u16 *)(1 << addr_bit)) != 0x5a5a) |
| 52 | return 0; // DRAM only one side. |
| 53 | return 1; // two sides. |
| 54 | } |
| 55 | |
| 56 | // DDRIII memory bank register control: |
| 57 | // bit : |
| 58 | // 2 - 0 : DRAMC_COLSIZE : DDRIII Column Address Type : 0 0 0 = 10bit |
| 59 | // : 0 0 1 = 11bit |
| 60 | // 7 - 5 : DRAMC_ROWSIZE : DDRIII Row Address Type : 0 0 0 = 13bit |
| 61 | // : 0 0 1 = 14bit |
| 62 | // : 0 1 0 = 15bit |
| 63 | // : 0 1 1 = 16bit |
| 64 | // 11 - 8 : DRAM_SIZE : DDRIII Size : 0 1 0 1 = 64M |
| 65 | // : 0 1 1 0 = 128M |
| 66 | // : 0 1 1 1 = 256M |
| 67 | // : 1 0 0 0 = 512M |
| 68 | // : 1 0 0 1 = 1GB |
| 69 | // : 1 0 1 0 = 2GB |
| 70 | // 13 : DRAMC_CSMASK : DDRIII CS#[1] Mask : 1 = Mask CS1 enable |
| 71 | |
| 72 | #define DDR3_COL_10BIT 0 |
| 73 | #define DDR3_COL_11BIT 1 |
| 74 | #define DDR3_ROW_13BIT 0 |
| 75 | #define DDR3_ROW_14BIT 1 |
| 76 | #define DDR3_ROW_15BIT 2 |
| 77 | #define DDR3_ROW_16BIT 3 |
| 78 | #define DDR3_SIZE_64M 5 |
| 79 | #define DDR3_SIZE_128M 6 |
| 80 | #define DDR3_SIZE_256M 7 |
| 81 | #define DDR3_SIZE_512M 8 |
| 82 | #define DDR3_SIZE_1GB 9 |
| 83 | #define DDR3_SIZE_2GB 10 |
| 84 | #define DDR3_C1M_ACTIVE 0 |
| 85 | #define DDR3_C1M_MASK 1 |
| 86 | |
| 87 | static u16 set_ddr3_mem_reg_col(u16 reg, u16 col) |
| 88 | { |
| 89 | return set_bitfield(reg, col, 3, 0); |
| 90 | } |
| 91 | |
| 92 | static u16 get_ddr3_mem_reg_col(u16 reg) |
| 93 | { |
| 94 | return get_bitfield(reg, 3, 0); |
| 95 | } |
| 96 | |
| 97 | static u16 set_ddr3_mem_reg_row(u16 reg, u16 row) |
| 98 | { |
| 99 | return set_bitfield(reg, row, 3, 5); |
| 100 | } |
| 101 | |
| 102 | static u16 get_ddr3_mem_reg_row(u16 reg) |
| 103 | { |
| 104 | return get_bitfield(reg, 3, 5); |
| 105 | } |
| 106 | |
| 107 | static u16 set_ddr3_mem_reg_size(u16 reg, u16 size) |
| 108 | { |
| 109 | return set_bitfield(reg, size, 4, 8); |
| 110 | } |
| 111 | |
| 112 | static u16 get_ddr3_mem_reg_size(u16 reg) |
| 113 | { |
| 114 | return get_bitfield(reg, 4, 8); |
| 115 | } |
| 116 | |
| 117 | static u16 set_ddr3_mem_reg_c1m(u16 reg, u16 c1m) |
| 118 | { |
| 119 | return set_bitfield(reg, c1m, 1, 13); |
| 120 | } |
| 121 | |
| 122 | static u16 get_ddr3_mem_reg_c1m(u16 reg) |
| 123 | { |
| 124 | return get_bitfield(reg, 1, 13); |
| 125 | } |
| 126 | |
| 127 | static u16 auto_set_ddr3_mem_reg_size(u16 reg) |
| 128 | { |
| 129 | u8 ss = 0; |
| 130 | // If reg is the minimum DRAM size, |
| 131 | // SS is also the minimum size 128M. |
| 132 | // If size in reg is bigger, SS is also bigger. |
| 133 | ss += get_ddr3_mem_reg_col(reg); |
| 134 | ss += get_ddr3_mem_reg_row(reg); |
| 135 | ss += (1 - get_ddr3_mem_reg_c1m(reg)); |
| 136 | ss += DDR3_SIZE_128M; |
| 137 | return set_ddr3_mem_reg_size(reg, ss); |
| 138 | } |
| 139 | |
| 140 | static u16 get_ddr3_mem_reg(u16 col, u16 row, u16 c1m) |
| 141 | { |
| 142 | u16 reg; |
| 143 | reg = 0; |
| 144 | reg = set_ddr3_mem_reg_col(reg, col); |
| 145 | reg = set_ddr3_mem_reg_row(reg, row); |
| 146 | reg = set_ddr3_mem_reg_c1m(reg, c1m); |
| 147 | reg = auto_set_ddr3_mem_reg_size(reg); |
| 148 | return reg; |
| 149 | } |
| 150 | |
| 151 | static void ddr3_phy_reset(void) |
| 152 | { |
| 153 | // PCI N/B reg FAh bit 6 = RST_DRAM_PHY. |
| 154 | pci_write_config8(NB1, NB1_REG_RESET_DRAMC_PHY, 0x40); |
| 155 | while ((pci_read_config8(NB1, NB1_REG_RESET_DRAMC_PHY) & 0x40) == 0x40) { |
| 156 | } |
| 157 | // reload mode. |
| 158 | u32 ddr3_cfg = pci_read_config32(NB, NB_REG_DDR3_CFG); |
| 159 | pci_write_config32(NB, NB_REG_DDR3_CFG, ddr3_cfg); |
| 160 | } |
| 161 | |
| 162 | static u8 detect_ddr3_dram_cs(u16 reg, u8 base_addr_bit) |
| 163 | { |
| 164 | reg = set_ddr3_mem_reg_c1m(reg, DDR3_C1M_ACTIVE); |
| 165 | reg = auto_set_ddr3_mem_reg_size(reg); |
| 166 | pci_write_config16(NB, NB_REG_MBR, reg); |
| 167 | if (check_dram_side(base_addr_bit + 1)) { |
| 168 | base_addr_bit += 1; |
| 169 | return 0; |
| 170 | } |
| 171 | |
| 172 | reg = set_ddr3_mem_reg_c1m(reg, DDR3_C1M_MASK); |
| 173 | reg = auto_set_ddr3_mem_reg_size(reg); |
| 174 | pci_write_config16(NB, NB_REG_MBR, reg); |
| 175 | // no need to check CS = 0. |
| 176 | // Need to reset DDR3 PHY. |
| 177 | ddr3_phy_reset(); |
| 178 | return 0; |
| 179 | } |
| 180 | |
| 181 | static u8 detect_ddr3_dram_row(u16 reg, u8 base_addr_bit) |
| 182 | { |
| 183 | reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_16BIT); |
| 184 | reg = auto_set_ddr3_mem_reg_size(reg); |
| 185 | pci_write_config16(NB, NB_REG_MBR, reg); |
| 186 | if (check_address_bit(base_addr_bit + 16)) { |
| 187 | base_addr_bit += 16; |
| 188 | return detect_ddr3_dram_cs(reg, base_addr_bit); |
| 189 | } |
| 190 | |
| 191 | reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_15BIT); |
| 192 | reg = auto_set_ddr3_mem_reg_size(reg); |
| 193 | pci_write_config16(NB, NB_REG_MBR, reg); |
| 194 | if (check_address_bit(base_addr_bit + 15)) { |
| 195 | base_addr_bit += 15; |
| 196 | return detect_ddr3_dram_cs(reg, base_addr_bit); |
| 197 | } |
| 198 | |
| 199 | reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_14BIT); |
| 200 | reg = auto_set_ddr3_mem_reg_size(reg); |
| 201 | pci_write_config16(NB, NB_REG_MBR, reg); |
| 202 | if (check_address_bit(base_addr_bit + 14)) { |
| 203 | base_addr_bit += 14; |
| 204 | return detect_ddr3_dram_cs(reg, base_addr_bit); |
| 205 | } |
| 206 | |
| 207 | reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_13BIT); |
| 208 | reg = auto_set_ddr3_mem_reg_size(reg); |
| 209 | pci_write_config16(NB, NB_REG_MBR, reg); |
| 210 | if (check_address_bit(base_addr_bit + 13)) { |
| 211 | base_addr_bit += 13; |
| 212 | return detect_ddr3_dram_cs(reg, base_addr_bit); |
| 213 | } |
| 214 | // row test error. |
| 215 | return 1; |
| 216 | } |
| 217 | |
| 218 | static u8 detect_ddr3_dram_bank(u16 reg, u8 base_addr_bit) |
| 219 | { |
| 220 | /* DDR3 is always 3 bank bits */ |
| 221 | base_addr_bit += 3; |
| 222 | return detect_ddr3_dram_row(reg, base_addr_bit); |
| 223 | } |
| 224 | |
| 225 | static u8 detect_ddr3_dram_col(u16 reg, u8 base_addr_bit) |
| 226 | { |
| 227 | reg = set_ddr3_mem_reg_col(reg, DDR3_COL_11BIT); |
| 228 | reg = auto_set_ddr3_mem_reg_size(reg); |
| 229 | pci_write_config16(NB, NB_REG_MBR, reg); |
| 230 | if (check_address_bit(base_addr_bit + 11)) { |
| 231 | base_addr_bit += 11; |
| 232 | return detect_ddr3_dram_bank(reg, base_addr_bit); |
| 233 | } |
| 234 | |
| 235 | reg = set_ddr3_mem_reg_col(reg, DDR3_COL_10BIT); |
| 236 | reg = auto_set_ddr3_mem_reg_size(reg); |
| 237 | pci_write_config16(NB, NB_REG_MBR, reg); |
| 238 | if (check_address_bit(base_addr_bit + 10)) { |
| 239 | base_addr_bit += 10; |
| 240 | return detect_ddr3_dram_bank(reg, base_addr_bit); |
| 241 | } |
| 242 | // col test error. |
| 243 | return 1; |
| 244 | } |
| 245 | |
| 246 | static u8 detect_ddr3_dram_size(void) |
| 247 | { |
| 248 | u16 reg; |
| 249 | u8 base_addr_bit = 0; |
| 250 | reg = get_ddr3_mem_reg(DDR3_COL_10BIT, DDR3_ROW_13BIT, DDR3_C1M_MASK); |
| 251 | return detect_ddr3_dram_col(reg, base_addr_bit); |
| 252 | } |
| 253 | |
| 254 | static void print_ddr3_memory_setup(void) |
| 255 | { |
| 256 | #if CONFIG_DEBUG_RAM_SETUP |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 257 | printk(BIOS_DEBUG, "DDR3 Timing Reg 0-3:\n"); |
| 258 | printk(BIOS_DEBUG, "NB 6e : "); |
Andrew Wu | 0651072 | 2013-06-21 21:37:05 +0800 | [diff] [blame] | 259 | print_debug_hex16(pci_read_config16(NB, 0x6e)); |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 260 | printk(BIOS_DEBUG, "\nNB 74 : "); |
Andrew Wu | 0651072 | 2013-06-21 21:37:05 +0800 | [diff] [blame] | 261 | print_debug_hex32(pci_read_config32(NB, 0x74)); |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 262 | printk(BIOS_DEBUG, "\nNB 78 : "); |
Andrew Wu | 0651072 | 2013-06-21 21:37:05 +0800 | [diff] [blame] | 263 | print_debug_hex32(pci_read_config32(NB, 0x78)); |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 264 | printk(BIOS_DEBUG, "\nNB 7c : "); |
Andrew Wu | 0651072 | 2013-06-21 21:37:05 +0800 | [diff] [blame] | 265 | print_debug_hex32(pci_read_config32(NB, 0x7c)); |
| 266 | u16 mbr = pci_read_config16(NB, 0x6c); |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 267 | printk(BIOS_DEBUG, "\nNB 6c(MBR) : "); |
Andrew Wu | 0651072 | 2013-06-21 21:37:05 +0800 | [diff] [blame] | 268 | print_debug_hex16(mbr); |
| 269 | const char *s; |
| 270 | u8 col = get_ddr3_mem_reg_col(mbr); |
| 271 | if (col == DDR3_COL_10BIT) |
| 272 | s = " (COL=10"; |
| 273 | else |
| 274 | s = " (COL=11"; |
| 275 | print_debug(s); |
| 276 | u8 row = get_ddr3_mem_reg_row(mbr); |
| 277 | switch (row) { |
| 278 | case DDR3_ROW_13BIT: |
| 279 | s = ", ROW = 13"; |
| 280 | break; |
| 281 | case DDR3_ROW_14BIT: |
| 282 | s = ", ROW = 14"; |
| 283 | break; |
| 284 | case DDR3_ROW_15BIT: |
| 285 | s = ", ROW = 15"; |
| 286 | break; |
| 287 | default: |
| 288 | s = ", ROW = 16"; |
| 289 | break; |
| 290 | } |
| 291 | print_debug(s); |
| 292 | u8 size = get_ddr3_mem_reg_size(mbr); |
| 293 | switch (size) { |
| 294 | case DDR3_SIZE_64M: |
| 295 | s = ", 64M"; |
| 296 | break; |
| 297 | case DDR3_SIZE_128M: |
| 298 | s = ", 128M"; |
| 299 | break; |
| 300 | case DDR3_SIZE_256M: |
| 301 | s = ", 256M"; |
| 302 | break; |
| 303 | case DDR3_SIZE_512M: |
| 304 | s = ", 512M"; |
| 305 | break; |
| 306 | case DDR3_SIZE_1GB: |
| 307 | s = ", 1GB"; |
| 308 | break; |
| 309 | case DDR3_SIZE_2GB: |
| 310 | s = ", 2GB"; |
| 311 | break; |
| 312 | } |
| 313 | print_debug(s); |
| 314 | u8 mask = get_ddr3_mem_reg_c1m(mbr); |
| 315 | if (mask == DDR3_C1M_ACTIVE) |
| 316 | s = ", CS MASK Enable)\n"; |
| 317 | else |
| 318 | s = ", CS Mask Disable)\n"; |
| 319 | print_debug(s); |
| 320 | #endif |
| 321 | } |