| Andrew Wu | 0651072 | 2013-06-21 21:37:05 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 DMP Electronics Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| Andrew Wu | 0651072 | 2013-06-21 21:37:05 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef NORTHBRIDGE_H |
| 17 | #define NORTHBRIDGE_H |
| 18 | |
| 19 | #define NB PCI_DEV(0, 0, 0) |
| 20 | #define NB_REG_SPI_BASE 0x40 |
| 21 | #define NB_REG_CLK_OUT_CTL 0x48 |
| 22 | #define NB_REG_PCI_CLK_CTL 0x4b |
| 23 | #define NB_REG_STRAP 0x60 |
| 24 | #define NB_REG_STRAP2 0x64 |
| 25 | #define NB_REG_MBR 0x6c |
| 26 | #define NB_REG_DDR3_CFG 0x74 |
| 27 | #define NB_REG_DDR3_MTR1 0x78 |
| 28 | #define NB_REG_DDR3_MTR2 0x7c |
| 29 | #define NB_REG_SMM 0x83 |
| 30 | #define NB_REG_MAR 0x84 |
| 31 | #define NB_REG_CID 0x90 |
| 32 | #define NB_REG_S1R 0x94 |
| 33 | #define NB_REG_S2R 0x98 |
| 34 | #define NB_REG_S3R 0x9c |
| 35 | #define NB_REG_HOST_CTL 0xa0 |
| 36 | #define NB_REG_CPU_MBCR 0xc4 |
| 37 | #define NB_REG_CDR 0xd0 |
| 38 | #define NB_REG_PACR 0xf0 |
| 39 | #define NB_REG_PMCR 0xf4 |
| 40 | #define NB_REG_PCI_TARGET 0xf8 |
| 41 | #define NB_REG_PCSCR 0xfc |
| 42 | |
| 43 | /* Additional "virtual" device, just extension of NB */ |
| 44 | #define NB1 PCI_DEV(0, 0, 1) |
| 45 | #define NB1_REG_FJZ_PHY_CTL1 0x80 |
| 46 | #define NB1_REG_FJZ_PHY_CTL2 0x84 |
| 47 | #define NB1_REG_FJZ_PHY_CTL3 0x88 |
| 48 | #define NB1_REG_FJZ_DRAM_CTL1 0x90 |
| 49 | #define NB1_REG_FJZ_DRAM_CTL2 0x94 |
| 50 | #define NB1_REG_FJZ_DRAM_CTL3 0x98 |
| 51 | #define NB1_REG_FJZ_DRAM_CTL4 0x9c |
| 52 | #define NB1_REG_PLL_TEST_CTL 0xa8 |
| 53 | #define NB1_REG_DDR3_PWR_SAV 0xbc |
| 54 | #define NB1_REG_DDR3_CTL_OPT1 0xc0 |
| 55 | #define NB1_REG_DDR3_CTL_OPT3 0xc8 |
| 56 | #define NB1_REG_DDR3_CTL_OPT4 0xcc |
| 57 | #define NB1_REG_DDR3_CTL_OPT5 0xce |
| 58 | #define NB1_REG_PLL_TEST_MODE 0xd0 |
| 59 | #define NB1_REG_L2_CACHE_CTL 0xe8 |
| 60 | #define NB1_REG_SSCR 0xec |
| 61 | #define NB1_REG_NB_CTL_OPT1 0xf4 |
| 62 | #define NB1_REG_UPDATE_PHY_IO 0xf8 |
| 63 | #define NB1_REG_RESET_DRAMC_PHY 0xfa |
| 64 | |
| 65 | #endif /* NORTHBRIDGE_H */ |