Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Jordan Crouse | b29209f | 2007-05-10 17:57:03 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Jordan Crouse | b29209f | 2007-05-10 17:57:03 +0000 | [diff] [blame] | 15 | */ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 16 | |
Christian Gmeiner | 194ec4d | 2013-06-04 14:30:50 +0200 | [diff] [blame] | 17 | #include "northbridge.h" |
| 18 | |
Patrick Georgi | 7dc2864 | 2012-07-13 19:06:22 +0200 | [diff] [blame] | 19 | static void pll_reset(void) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 20 | { |
| 21 | msr_t msrGlcpSysRstpll; |
| 22 | |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 23 | msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL); |
| 24 | |
Stefan Reinauer | b9aea89 | 2010-04-20 15:49:59 +0000 | [diff] [blame] | 25 | printk(BIOS_DEBUG, "MSR GLCP_SYS_RSTPLL (%08x) value is %08x:%08x\n", |
| 26 | GLCP_SYS_RSTPLL, msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo); |
| 27 | |
Stefan Reinauer | 0c781b2 | 2010-04-01 09:50:32 +0000 | [diff] [blame] | 28 | post_code(POST_PLL_INIT); |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 29 | |
| 30 | if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { |
Stefan Reinauer | b9aea89 | 2010-04-20 15:49:59 +0000 | [diff] [blame] | 31 | printk(BIOS_DEBUG, "Configuring PLL.\n"); |
Patrick Georgi | 7dc2864 | 2012-07-13 19:06:22 +0200 | [diff] [blame] | 32 | if (CONFIG_PLL_MANUAL_CONFIG) { |
Stefan Reinauer | 0c781b2 | 2010-04-01 09:50:32 +0000 | [diff] [blame] | 33 | post_code(POST_PLL_MANUAL); |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 34 | /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ |
Patrick Georgi | 7dc2864 | 2012-07-13 19:06:22 +0200 | [diff] [blame] | 35 | msrGlcpSysRstpll.hi = CONFIG_PLLMSRhi; |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 36 | |
| 37 | /* Hold Count - how long we will sit in reset */ |
Patrick Georgi | 7dc2864 | 2012-07-13 19:06:22 +0200 | [diff] [blame] | 38 | msrGlcpSysRstpll.lo = CONFIG_PLLMSRlo; |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 39 | } else { |
| 40 | /*automatic configuration (straps) */ |
Stefan Reinauer | 0c781b2 | 2010-04-01 09:50:32 +0000 | [diff] [blame] | 41 | post_code(POST_PLL_STRAP); |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 42 | msrGlcpSysRstpll.lo &= |
| 43 | ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT); |
| 44 | msrGlcpSysRstpll.lo |= |
| 45 | (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT); |
| 46 | msrGlcpSysRstpll.lo &= |
| 47 | ~(RSTPPL_LOWER_COREBYPASS_SET | |
| 48 | RSTPPL_LOWER_MBBYPASS_SET); |
| 49 | msrGlcpSysRstpll.lo |= |
| 50 | RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET; |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 51 | } |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 52 | /* Use SWFLAGS to remember: "we've already been here" */ |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 53 | msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT); |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 54 | |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 55 | /* "reset the chip" value */ |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 56 | msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 57 | wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 58 | |
Stefan Reinauer | b9aea89 | 2010-04-20 15:49:59 +0000 | [diff] [blame] | 59 | /* You should never get here..... The chip has reset. */ |
Stefan Reinauer | 0c781b2 | 2010-04-01 09:50:32 +0000 | [diff] [blame] | 60 | post_code(POST_PLL_RESET_FAIL); |
Nils Jacobs | 8cf54c9 | 2010-12-30 19:21:08 +0000 | [diff] [blame] | 61 | die("CONFIGURING PLL FAILURE\n"); |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 62 | |
| 63 | } |
Stefan Reinauer | b9aea89 | 2010-04-20 15:49:59 +0000 | [diff] [blame] | 64 | printk(BIOS_DEBUG, "PLL configured.\n"); |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 65 | return; |
| 66 | } |
| 67 | |
Stefan Reinauer | 720297c | 2010-04-02 22:11:20 +0000 | [diff] [blame] | 68 | #if 0 // Unused |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 69 | static unsigned int CPUSpeed(void) |
| 70 | { |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 71 | unsigned int speed; |
| 72 | msr_t msr; |
| 73 | |
| 74 | msr = rdmsr(GLCP_SYS_RSTPLL); |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 75 | speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10; |
| 76 | if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) { |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 77 | ++speed; |
| 78 | } |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 79 | return (speed); |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 80 | } |
Stefan Reinauer | 720297c | 2010-04-02 22:11:20 +0000 | [diff] [blame] | 81 | #endif |
| 82 | |
Christian Gmeiner | 194ec4d | 2013-06-04 14:30:50 +0200 | [diff] [blame] | 83 | unsigned int GeodeLinkSpeed(void) |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 84 | { |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 85 | unsigned int speed; |
| 86 | msr_t msr; |
| 87 | |
| 88 | msr = rdmsr(GLCP_SYS_RSTPLL); |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 89 | speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10; |
| 90 | if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) { |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 91 | ++speed; |
| 92 | } |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 93 | return (speed); |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 94 | } |
Stefan Reinauer | 720297c | 2010-04-02 22:11:20 +0000 | [diff] [blame] | 95 | |
| 96 | #if 0 // Unused |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 97 | static unsigned int PCISpeed(void) |
| 98 | { |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 99 | msr_t msr; |
| 100 | |
| 101 | msr = rdmsr(GLCP_SYS_RSTPLL); |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 102 | if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) { |
| 103 | return (66); |
| 104 | } else { |
| 105 | return (33); |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 106 | } |
| 107 | } |
Stefan Reinauer | 720297c | 2010-04-02 22:11:20 +0000 | [diff] [blame] | 108 | #endif |