Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Jordan Crouse | b29209f | 2007-05-10 17:57:03 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Jordan Crouse | b29209f | 2007-05-10 17:57:03 +0000 | [diff] [blame] | 15 | */ |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 16 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 17 | #include <console/console.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <stdint.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <stdlib.h> |
| 24 | #include <string.h> |
Indrek Kruusa | 8e34641 | 2006-08-03 16:48:18 +0000 | [diff] [blame] | 25 | #include <cpu/cpu.h> |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 26 | #include <cpu/amd/lxdef.h> |
| 27 | #include <cpu/x86/msr.h> |
| 28 | #include <cpu/x86/cache.h> |
| 29 | #include <cpu/amd/vr.h> |
Corey Osgood | e562f72 | 2008-12-19 03:36:48 +0000 | [diff] [blame] | 30 | #include <cpu/cpu.h> |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 31 | #include "northbridge.h" |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 32 | #include "../../../southbridge/amd/cs5536/cs5536.h" |
| 33 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 34 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 35 | /* here is programming for the various MSRs.*/ |
| 36 | #define IM_QWAIT 0x100000 |
| 37 | |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 38 | #define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */ |
| 39 | #define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 40 | |
| 41 | /* these are the 8-bit attributes for controlling RCONF registers */ |
| 42 | #define CACHE_DISABLE (1<<0) |
| 43 | #define WRITE_ALLOCATE (1<<1) |
| 44 | #define WRITE_PROTECT (1<<2) |
| 45 | #define WRITE_THROUGH (1<<3) |
| 46 | #define WRITE_COMBINE (1<<4) |
| 47 | #define WRITE_SERIALIZE (1<<5) |
| 48 | |
| 49 | /* ram has none of this stuff */ |
| 50 | #define RAM_PROPERTIES (0) |
| 51 | #define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE) |
| 52 | #define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE) |
| 53 | #define MSR_WS_CD_DEFAULT (0x21212121) |
| 54 | |
| 55 | /* 1810-1817 give you 8 registers with which to program protection regions */ |
| 56 | /* the are region configuration range registers, or RRCF */ |
| 57 | /* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */ |
| 58 | /* so no left-shift needed for top or base */ |
| 59 | #define RRCF_LOW(base,properties) (base|(1<<8)|properties) |
| 60 | #define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE) |
| 61 | |
| 62 | /* build initializer for P2D MSR */ |
| 63 | #define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}} |
| 64 | #define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}} |
| 65 | #define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}} |
| 66 | #define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}} |
| 67 | #define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}} |
| 68 | #define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}} |
| 69 | #define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}} |
| 70 | |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 71 | void print_conf(void); |
| 72 | void graphics_init(void); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 73 | void do_vsmbios(void); |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 74 | |
| 75 | struct msr_defaults { |
| 76 | int msr_no; |
| 77 | msr_t msr; |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 78 | } msr_defaults[] = { |
| 79 | { |
| 80 | 0x1700, { |
| 81 | .hi = 0,.lo = IM_QWAIT}}, { |
| 82 | 0x1800, { |
| 83 | .hi = DMCF_WRITE_SERIALIZE_REQUEST,.lo = |
| 84 | DMCF_SERIAL_LOAD_MISSES}}, |
| 85 | /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */ |
| 86 | /* for 180a, for now, we assume VSM will configure it */ |
| 87 | /* 180b is left at reset value,a0000-bffff is non-cacheable */ |
| 88 | /* 180c, c0000-dffff is set to write serialize and non-cachable */ |
| 89 | /* oops, 180c will be set by cpu bug handling in cpubug.c */ |
| 90 | //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, |
| 91 | /* 180d is left at default, e0000-fffff is non-cached */ |
| 92 | /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ |
| 93 | /* we will not set 0x180f, the DMM,yet */ |
| 94 | //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, |
| 95 | //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, |
| 96 | //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, |
| 97 | //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, |
| 98 | /* now for GLPCI routing */ |
| 99 | /* GLIU0 */ |
| 100 | P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80), |
| 101 | P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), |
| 102 | P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), |
| 103 | /* GLIU1 */ |
| 104 | P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80), |
| 105 | P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), |
| 106 | P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), { |
| 107 | 0} |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 108 | }; |
| 109 | |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 110 | /* Print the platform configuration - do before PCI init or it will not |
| 111 | * work right. |
| 112 | */ |
| 113 | void print_conf(void) |
| 114 | { |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 115 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 116 | int i; |
| 117 | unsigned long iol; |
| 118 | msr_t msr; |
| 119 | |
| 120 | int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0, |
| 121 | CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, |
| 122 | CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM, |
| 123 | GLCP_DELAY_CONTROLS, GL_END |
| 124 | }; |
| 125 | |
| 126 | int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, |
| 127 | MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6, |
| 128 | GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM, |
| 129 | GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, |
| 130 | MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, |
| 131 | GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, |
| 132 | GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5, |
| 133 | GLIU0_GLD_MSR_COH, GL_END |
| 134 | }; |
| 135 | |
| 136 | int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, |
| 137 | MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, |
| 138 | MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, |
| 139 | MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0, |
| 140 | GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW, |
| 141 | GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0, |
| 142 | GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, |
| 143 | GLIU1_GLD_MSR_COH, GL_END |
| 144 | }; |
| 145 | |
| 146 | int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, |
| 147 | CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END |
| 148 | }; |
| 149 | |
| 150 | int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, |
| 151 | MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, |
| 152 | MDD_IRQM_PRIM, GL_END |
| 153 | }; |
| 154 | |
| 155 | int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, |
| 156 | GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, |
| 157 | GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END |
| 158 | }; |
| 159 | |
| 160 | int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, |
| 161 | MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6, |
| 162 | MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END |
| 163 | }; |
| 164 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 165 | printk(BIOS_DEBUG, "---------- CPU ------------\n"); |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 166 | |
| 167 | for (i = 0; cpu_msr_defs[i] != GL_END; i++) { |
| 168 | msr = rdmsr(cpu_msr_defs[i]); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 169 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 170 | cpu_msr_defs[i], msr.hi, msr.lo); |
| 171 | } |
| 172 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 173 | printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n"); |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 174 | |
| 175 | for (i = 0; gliu0_msr_defs[i] != GL_END; i++) { |
| 176 | msr = rdmsr(gliu0_msr_defs[i]); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 177 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 178 | gliu0_msr_defs[i], msr.hi, msr.lo); |
| 179 | } |
| 180 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 181 | printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n"); |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 182 | |
| 183 | for (i = 0; gliu1_msr_defs[i] != GL_END; i++) { |
| 184 | msr = rdmsr(gliu1_msr_defs[i]); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 185 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 186 | gliu1_msr_defs[i], msr.hi, msr.lo); |
| 187 | } |
| 188 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 189 | printk(BIOS_DEBUG, "---------- RCONF ------------\n"); |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 190 | |
| 191 | for (i = 0; rconf_msr[i] != GL_END; i++) { |
| 192 | msr = rdmsr(rconf_msr[i]); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 193 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 194 | msr.hi, msr.lo); |
| 195 | } |
| 196 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 197 | printk(BIOS_DEBUG, "---------- VARIA ------------\n"); |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 198 | msr = rdmsr(0x51300010); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 199 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 200 | msr.lo); |
| 201 | |
| 202 | msr = rdmsr(0x51400015); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 203 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 204 | msr.lo); |
| 205 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 206 | printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n"); |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 207 | msr = rdmsr(MDD_IRQM_YLOW); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 208 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 209 | msr.lo); |
| 210 | msr = rdmsr(MDD_IRQM_YHIGH); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 211 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 212 | msr.hi, msr.lo); |
| 213 | msr = rdmsr(MDD_IRQM_ZLOW); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 214 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 215 | msr.lo); |
| 216 | msr = rdmsr(MDD_IRQM_ZHIGH); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 217 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 218 | msr.hi, msr.lo); |
| 219 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 220 | printk(BIOS_DEBUG, "---------- PCI ------------\n"); |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 221 | |
| 222 | for (i = 0; pci_msr[i] != GL_END; i++) { |
| 223 | msr = rdmsr(pci_msr[i]); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 224 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 225 | msr.hi, msr.lo); |
| 226 | } |
| 227 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 228 | printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n"); |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 229 | |
| 230 | for (i = 0; dma_msr[i] != GL_END; i++) { |
| 231 | msr = rdmsr(dma_msr[i]); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 232 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 233 | msr.hi, msr.lo); |
| 234 | } |
| 235 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 236 | printk(BIOS_DEBUG, "---------- CS5536 ------------\n"); |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 237 | |
| 238 | for (i = 0; cs5536_msr[i] != GL_END; i++) { |
| 239 | msr = rdmsr(cs5536_msr[i]); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 240 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 241 | msr.hi, msr.lo); |
| 242 | } |
| 243 | |
| 244 | iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 245 | printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 246 | GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol); |
| 247 | iol = inl(GPIOL_EVENTS_ENABLE); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 248 | printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 249 | GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol); |
| 250 | iol = inl(GPIOL_INPUT_INVERT_ENABLE); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 251 | printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 252 | GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol); |
| 253 | iol = inl(GPIO_MAPPER_X); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 254 | printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X, |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 255 | iol); |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 256 | #endif //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR |
Carl-Daniel Hailfinger | cb5c9fb | 2008-02-05 09:21:46 +0000 | [diff] [blame] | 257 | } |
| 258 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 259 | /* todo: add a resource record. We don't do this here because this may be called when |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 260 | * very little of the platform is actually working. |
| 261 | */ |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 262 | int sizeram(void) |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 263 | { |
| 264 | msr_t msr; |
| 265 | int sizem = 0; |
| 266 | unsigned short dimm; |
| 267 | |
Marc Jones | ddf845f | 2007-05-10 23:22:27 +0000 | [diff] [blame] | 268 | /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */ |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 269 | msr = rdmsr(MC_CF07_DATA); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 270 | printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 271 | |
| 272 | /* dimm 0 */ |
| 273 | dimm = msr.hi; |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 274 | /* installed? */ |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 275 | if ((dimm & 7) != 7) { |
Marc Jones | ddf845f | 2007-05-10 23:22:27 +0000 | [diff] [blame] | 276 | sizem = 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 277 | } |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 278 | |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 279 | /* dimm 1 */ |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 280 | dimm = msr.hi >> 16; |
| 281 | /* installed? */ |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 282 | if ((dimm & 7) != 7) { |
Marc Jones | ddf845f | 2007-05-10 23:22:27 +0000 | [diff] [blame] | 283 | sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 284 | } |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 285 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 286 | printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 287 | return sizem; |
| 288 | } |
| 289 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 290 | static void enable_shadow(device_t dev) |
| 291 | { |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 292 | } |
| 293 | |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 294 | static void northbridge_init(device_t dev) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 295 | { |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 296 | //msr_t msr; |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 297 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 298 | printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 299 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 300 | enable_shadow(dev); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 301 | /* |
| 302 | * Swiss cheese |
| 303 | */ |
| 304 | //msr = rdmsr(MSR_GLIU0_SHADOW); |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 305 | |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 306 | //msr.hi |= 0x3; |
| 307 | //msr.lo |= 0x30000; |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 308 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 309 | //printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo); |
| 310 | //printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 311 | } |
| 312 | |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 313 | static void northbridge_set_resources(struct device *dev) |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 314 | { |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 315 | uint8_t line; |
| 316 | |
Myles Watson | c25cc11 | 2010-05-21 14:33:48 +0000 | [diff] [blame] | 317 | #if 0 |
| 318 | struct resource *res; |
| 319 | for (res = dev->resource_list; res; res = res->next) { |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 320 | |
| 321 | // andrei: do not change the base address, it will make the VSA virtual registers unusable |
Myles Watson | c25cc11 | 2010-05-21 14:33:48 +0000 | [diff] [blame] | 322 | //pci_set_resource(dev, res); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 323 | // FIXME: static allocation may conflict with dynamic mappings! |
| 324 | } |
Myles Watson | c25cc11 | 2010-05-21 14:33:48 +0000 | [diff] [blame] | 325 | #endif |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 326 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 327 | struct bus *bus; |
| 328 | for (bus = dev->link_list; bus; bus = bus->next) { |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 329 | if (bus->children) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 330 | printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n", |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 331 | bus->secondary); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 332 | assign_resources(bus); |
| 333 | } |
| 334 | } |
| 335 | |
| 336 | /* set a default latency timer */ |
| 337 | pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); |
| 338 | |
| 339 | /* set a default secondary latency timer */ |
| 340 | if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { |
| 341 | pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40); |
| 342 | } |
| 343 | |
| 344 | /* zero the irq settings */ |
| 345 | line = pci_read_config8(dev, PCI_INTERRUPT_PIN); |
| 346 | if (line) { |
| 347 | pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); |
| 348 | } |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 349 | |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 350 | /* set the cache line size, so far 64 bytes is good for everyone */ |
| 351 | pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 352 | } |
| 353 | |
| 354 | static struct device_operations northbridge_operations = { |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 355 | .read_resources = pci_dev_read_resources, |
| 356 | .set_resources = northbridge_set_resources, |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 357 | .enable_resources = pci_dev_enable_resources, |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 358 | .init = northbridge_init, |
| 359 | .enable = 0, |
| 360 | .ops_pci = 0, |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 361 | }; |
| 362 | |
Stefan Reinauer | f1cf1f7 | 2007-10-24 09:08:58 +0000 | [diff] [blame] | 363 | static const struct pci_driver northbridge_driver __pci_driver = { |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 364 | .ops = &northbridge_operations, |
| 365 | .vendor = PCI_VENDOR_ID_AMD, |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 366 | .device = PCI_DEVICE_ID_AMD_LXBRIDGE, |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 367 | }; |
| 368 | |
Rudolf Marek | 97be27e | 2010-12-13 19:50:25 +0000 | [diff] [blame] | 369 | #include <cbmem.h> |
Stefan Reinauer | b5fb0c5 | 2009-04-30 13:58:42 +0000 | [diff] [blame] | 370 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 371 | static void pci_domain_set_resources(device_t dev) |
| 372 | { |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 373 | int idx; |
Stefan Reinauer | b5fb0c5 | 2009-04-30 13:58:42 +0000 | [diff] [blame] | 374 | u32 tomk; |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 375 | device_t mc_dev; |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 376 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 377 | printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 378 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 379 | mc_dev = dev->link_list->children; |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 380 | if (mc_dev) { |
Christian Gmeiner | e2dc80c | 2013-06-04 16:23:43 +0200 | [diff] [blame] | 381 | tomk = get_top_of_ram() / 1024; |
Edwin Beasant | 87d0c54 | 2010-01-27 18:19:33 +0000 | [diff] [blame] | 382 | /* Report the memory regions |
| 383 | All memory up to systop except 0xa0000-0xbffff */ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 384 | idx = 10; |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 385 | ram_resource(dev, idx++, 0, 640); |
Edwin Beasant | 87d0c54 | 2010-01-27 18:19:33 +0000 | [diff] [blame] | 386 | ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB |
Stefan Reinauer | b5fb0c5 | 2009-04-30 13:58:42 +0000 | [diff] [blame] | 387 | |
Kyösti Mälkki | 42f4651 | 2013-06-27 08:20:09 +0300 | [diff] [blame] | 388 | set_top_of_ram(tomk * 1024); |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 389 | } |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 390 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 391 | assign_resources(dev->link_list); |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 392 | } |
| 393 | |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 394 | static void pci_domain_enable(device_t dev) |
| 395 | { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 396 | printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 397 | |
| 398 | // do this here for now -- this chip really breaks our device model |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 399 | northbridge_init_early(); |
| 400 | cpubug(); |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 401 | chipsetinit(); |
| 402 | |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 403 | // print_conf(); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 404 | |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 405 | do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;) |
| 406 | |
Marc Jones | 734daf6 | 2007-05-04 18:58:42 +0000 | [diff] [blame] | 407 | // print_conf(); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 408 | |
| 409 | graphics_init(); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 410 | } |
| 411 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 412 | static struct device_operations pci_domain_ops = { |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 413 | .read_resources = pci_domain_read_resources, |
| 414 | .set_resources = pci_domain_set_resources, |
Myles Watson | 7eac445 | 2010-06-17 16:16:56 +0000 | [diff] [blame] | 415 | .enable_resources = NULL, |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 416 | .scan_bus = pci_domain_scan_bus, |
| 417 | .enable = pci_domain_enable, |
Kyösti Mälkki | 33e5df3 | 2013-07-03 10:51:34 +0300 | [diff] [blame] | 418 | .ops_pci_bus = pci_bus_default_ops, |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 419 | }; |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 420 | |
| 421 | static void cpu_bus_init(device_t dev) |
| 422 | { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 423 | printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 424 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 425 | initialize_cpus(dev->link_list); |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 426 | } |
| 427 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 428 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 812d2a4 | 2014-10-31 08:17:23 +1100 | [diff] [blame] | 429 | .read_resources = DEVICE_NOOP, |
| 430 | .set_resources = DEVICE_NOOP, |
| 431 | .enable_resources = DEVICE_NOOP, |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 432 | .init = cpu_bus_init, |
| 433 | .scan_bus = 0, |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 434 | }; |
| 435 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 436 | static void enable_dev(struct device *dev) |
| 437 | { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 438 | printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n", |
Myles Watson | 552b327 | 2009-02-12 21:30:06 +0000 | [diff] [blame] | 439 | __func__, dev->path.type); |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 440 | |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 441 | /* Set the operations if it is a special bus type */ |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 442 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 443 | dev->ops = &pci_domain_ops; |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 444 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 445 | dev->ops = &cpu_bus_ops; |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 446 | } |
| 447 | |
| 448 | struct chip_operations northbridge_amd_lx_ops = { |
| 449 | CHIP_NAME("AMD LX Northbridge") |
Jordan Crouse | f8030bd | 2007-05-10 18:16:03 +0000 | [diff] [blame] | 450 | .enable_dev = enable_dev, |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 451 | }; |