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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / northbridge / amd / amdk8 / f_pci.c
blob: d89dadc0d626b670aab0b2393c501a6993cab3ed [file] [log] [blame]
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]1#ifndef AMDK8_F_PCI_C
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]2#define AMDK8_F_PCI_C
Stefan Reinauer116ec612010-04-23 19:16:30 +0000[diff] [blame]3
4#ifdef UNUSED_CODE
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]5/* bit [10,8] are dev func, bit[1,0] are dev index */
6static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index)
7{
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]8 uint32_t dword;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]9
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]10 pci_write_config32(dev, index_reg, index);
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]11
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]12 dword = pci_read_config32(dev, index_reg+0x4);
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]13
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]14 return dword;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]15}
16
17static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
18{
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]19 pci_write_config32(dev, index_reg, index);
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]20
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]21 pci_write_config32(dev, index_reg + 0x4, data);
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]22}
Stefan Reinauer116ec612010-04-23 19:16:30 +0000[diff] [blame]23#endif
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]24
25static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index)
26{
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]27 uint32_t dword;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]28
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]29 index &= ~(1<<30);
30 pci_write_config32(dev, index_reg, index);
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]31
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]32 do {
33 dword = pci_read_config32(dev, index_reg);
34 } while (!(dword & (1<<31)));
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]35
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]36 dword = pci_read_config32(dev, index_reg+0x4);
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]37
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]38 return dword;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]39}
40
41static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
42{
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]43 uint32_t dword;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]44
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]45 pci_write_config32(dev, index_reg + 0x4, data);
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]46
Myles Watsond61ada62008-10-02 19:20:22 +0000[diff] [blame]47 index |= (1<<30);
48 pci_write_config32(dev, index_reg, index);
49 do {
50 dword = pci_read_config32(dev, index_reg);
51 } while (!(dword & (1<<31)));
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]52}
53
54#endif