Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 1 | #ifndef AMDK8_F_H |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 2 | #define AMDK8_F_H |
Stefan Reinauer | 5e33e82 | 2010-07-07 21:59:06 +0000 | [diff] [blame] | 3 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 4 | /* Definitions of various K8 registers */ |
| 5 | /* Function 0 */ |
| 6 | #define HT_TRANSACTION_CONTROL 0x68 |
| 7 | #define HTTC_DIS_RD_B_P (1 << 0) |
| 8 | #define HTTC_DIS_RD_DW_P (1 << 1) |
| 9 | #define HTTC_DIS_WR_B_P (1 << 2) |
| 10 | #define HTTC_DIS_WR_DW_P (1 << 3) |
| 11 | #define HTTC_DIS_MTS (1 << 4) |
| 12 | #define HTTC_CPU1_EN (1 << 5) |
| 13 | #define HTTC_CPU_REQ_PASS_PW (1 << 6) |
| 14 | #define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) |
| 15 | #define HTTC_DIS_P_MEM_C (1 << 8) |
| 16 | #define HTTC_DIS_RMT_MEM_C (1 << 9) |
| 17 | #define HTTC_DIS_FILL_P (1 << 10) |
| 18 | #define HTTC_RSP_PASS_PW (1 << 11) |
| 19 | #define HTTC_CHG_ISOC_TO_ORD (1 << 12) |
| 20 | #define HTTC_BUF_REL_PRI_SHIFT 13 |
| 21 | #define HTTC_BUF_REL_PRI_MASK 3 |
| 22 | #define HTTC_BUF_REL_PRI_64 0 |
| 23 | #define HTTC_BUF_REL_PRI_16 1 |
| 24 | #define HTTC_BUF_REL_PRI_8 2 |
| 25 | #define HTTC_BUF_REL_PRI_2 3 |
| 26 | #define HTTC_LIMIT_CLDT_CFG (1 << 15) |
| 27 | #define HTTC_LINT_EN (1 << 16) |
| 28 | #define HTTC_APIC_EXT_BRD_CST (1 << 17) |
| 29 | #define HTTC_APIC_EXT_ID (1 << 18) |
| 30 | #define HTTC_APIC_EXT_SPUR (1 << 19) |
| 31 | #define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) |
| 32 | #define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 |
| 33 | #define HTTC_DS_NP_REQ_LIMIT_MASK 3 |
| 34 | #define HTTC_DS_NP_REQ_LIMIT_NONE 0 |
| 35 | #define HTTC_DS_NP_REQ_LIMIT_1 1 |
| 36 | #define HTTC_DS_NP_REQ_LIMIT_4 2 |
| 37 | #define HTTC_DS_NP_REQ_LIMIT_8 3 |
| 38 | #define HTTC_MED_PRI_BYP_CNT_SHIFT 24 |
| 39 | #define HTTC_MED_PRI_BYP_CNT_MASK 3 |
| 40 | #define HTTC_HI_PRI_BYP_CNT_SHIFT 26 |
| 41 | #define HTTC_HI_PRI_BYP_CNT_MASK 3 |
| 42 | |
| 43 | |
| 44 | /* Function 1 */ |
| 45 | #define PCI_IO_BASE0 0xc0 |
| 46 | #define PCI_IO_BASE1 0xc8 |
| 47 | #define PCI_IO_BASE2 0xd0 |
| 48 | #define PCI_IO_BASE3 0xd8 |
| 49 | #define PCI_IO_BASE_VGA_EN (1 << 4) |
| 50 | #define PCI_IO_BASE_NO_ISA (1 << 5) |
| 51 | |
| 52 | |
| 53 | /* Function 2 */ |
| 54 | #define DRAM_CSBASE 0x40 |
| 55 | #define DRAM_CSMASK 0x60 |
| 56 | #define DRAM_BANK_ADDR_MAP 0x80 |
| 57 | |
| 58 | #define DRAM_CTRL 0x78 |
| 59 | #define DC_RdPtrInit_SHIFT 0 |
| 60 | #define DC_RdPrtInit_MASK 0xf |
| 61 | #define DC_RdPadRcvFifoDly_SHIFT 4 |
| 62 | #define DC_RdPadRcvFifoDly_MASK 7 |
| 63 | #define DC_RdPadRcvFiloDly_1_5_CLK 2 |
| 64 | #define DC_RdPadRcvFiloDly_2_CLK 3 |
| 65 | #define DC_RdPadRcvFiloDly_2_5_CLK 4 |
| 66 | #define DC_RdPadRcvFiloDly_3_CLK 5 |
| 67 | #define DC_RdPadRcvFiloDly_3_5_CLK 6 |
| 68 | #define DC_AltVidC3MemClkTriEn (1<<16) |
| 69 | #define DC_DllTempAdjTime_SHIFT 17 |
| 70 | #define DC_DllTempAdjTime_MASK 1 |
| 71 | #define DC_DllTempAdjTime_5_MS 0 |
| 72 | #define DC_DllTempAdjTime_1_MS 1 |
| 73 | #define DC_DqsRcvEnTrain (1<<18) |
| 74 | |
| 75 | #define DRAM_INIT 0x7c |
| 76 | #define DI_MrsAddress_SHIFT 0 |
| 77 | #define DI_MrsAddress_MASK 0xffff |
| 78 | #define DI_MrsBank_SHIFT 16 |
| 79 | #define DI_MrsBank_MASK 7 |
| 80 | #define DI_SendRchgAll (1<<24) |
| 81 | #define DI_SendAutoRefresh (1<<25) |
| 82 | #define DI_SendMrsCmd (1<<26) |
| 83 | #define DI_DeassertMemRstX (1<<27) |
| 84 | #define DI_AssertCke (1<<28) |
| 85 | #define DI_EnDramInit (1<<31) |
| 86 | |
| 87 | #define DRAM_TIMING_LOW 0x88 |
| 88 | #define DTL_TCL_SHIFT 0 |
| 89 | #define DTL_TCL_MASK 7 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 90 | #define DTL_TCL_BASE 1 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 91 | #define DTL_TCL_MIN 3 |
| 92 | #define DTL_TCL_MAX 6 |
| 93 | #define DTL_TRCD_SHIFT 4 |
| 94 | #define DTL_TRCD_MASK 3 |
| 95 | #define DTL_TRCD_BASE 3 |
| 96 | #define DTL_TRCD_MIN 3 |
| 97 | #define DTL_TRCD_MAX 6 |
| 98 | #define DTL_TRP_SHIFT 8 |
| 99 | #define DTL_TRP_MASK 3 |
| 100 | #define DTL_TRP_BASE 3 |
| 101 | #define DTL_TRP_MIN 3 |
| 102 | #define DTL_TRP_MAX 6 |
| 103 | #define DTL_TRTP_SHIFT 11 |
| 104 | #define DTL_TRTP_MASK 1 |
| 105 | #define DTL_TRTP_BASE 2 |
| 106 | #define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/ |
| 107 | #define DTL_TRTP_MAX 3 /* 5 for 64 bytes */ |
| 108 | #define DTL_TRAS_SHIFT 12 |
| 109 | #define DTL_TRAS_MASK 0xf |
| 110 | #define DTL_TRAS_BASE 3 |
| 111 | #define DTL_TRAS_MIN 5 |
| 112 | #define DTL_TRAS_MAX 18 |
| 113 | #define DTL_TRC_SHIFT 16 |
| 114 | #define DTL_TRC_MASK 0xf |
| 115 | #define DTL_TRC_BASE 11 |
| 116 | #define DTL_TRC_MIN 11 |
| 117 | #define DTL_TRC_MAX 26 |
| 118 | #define DTL_TWR_SHIFT 20 |
| 119 | #define DTL_TWR_MASK 3 |
| 120 | #define DTL_TWR_BASE 3 |
| 121 | #define DTL_TWR_MIN 3 |
| 122 | #define DTL_TWR_MAX 6 |
| 123 | #define DTL_TRRD_SHIFT 22 |
| 124 | #define DTL_TRRD_MASK 3 |
| 125 | #define DTL_TRRD_BASE 2 |
| 126 | #define DTL_TRRD_MIN 2 |
| 127 | #define DTL_TRRD_MAX 5 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 128 | #define DTL_MemClkDis_SHIFT 24 /* Channel A */ |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 129 | #define DTL_MemClkDis3 (1 << 26) |
| 130 | #define DTL_MemClkDis2 (1 << 27) |
| 131 | #define DTL_MemClkDis1 (1 << 28) |
| 132 | #define DTL_MemClkDis0 (1 << 29) |
| 133 | #define DTL_MemClkDis1_AM2 (0x51 << 24) |
| 134 | #define DTL_MemClkDis0_AM2 (0xa2 << 24) |
| 135 | #define DTL_MemClkDis0_S1g1 (0xa2 << 24) |
| 136 | |
| 137 | /* DTL_MemClkDis for m2 and s1g1 is different */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 138 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 139 | #define DRAM_TIMING_HIGH 0x8c |
| 140 | #define DTH_TRWTTO_SHIFT 4 |
| 141 | #define DTH_TRWTTO_MASK 7 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 142 | #define DTH_TRWTTO_BASE 2 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 143 | #define DTH_TRWTTO_MIN 2 |
| 144 | #define DTH_TRWTTO_MAX 9 |
| 145 | #define DTH_TWTR_SHIFT 8 |
| 146 | #define DTH_TWTR_MASK 3 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 147 | #define DTH_TWTR_BASE 0 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 148 | #define DTH_TWTR_MIN 1 |
| 149 | #define DTH_TWTR_MAX 3 |
| 150 | #define DTH_TWRRD_SHIFT 10 |
| 151 | #define DTH_TWRRD_MASK 3 |
| 152 | #define DTH_TWRRD_BASE 0 |
| 153 | #define DTH_TWRRD_MIN 0 |
| 154 | #define DTH_TWRRD_MAX 3 |
| 155 | #define DTH_TWRWR_SHIFT 12 |
| 156 | #define DTH_TWRWR_MASK 3 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 157 | #define DTH_TWRWR_BASE 1 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 158 | #define DTH_TWRWR_MIN 1 |
| 159 | #define DTH_TWRWR_MAX 3 |
| 160 | #define DTH_TRDRD_SHIFT 14 |
| 161 | #define DTH_TRDRD_MASK 3 |
| 162 | #define DTH_TRDRD_BASE 2 |
| 163 | #define DTH_TRDRD_MIN 2 |
| 164 | #define DTH_TRDRD_MAX 5 |
| 165 | #define DTH_TREF_SHIFT 16 |
| 166 | #define DTH_TREF_MASK 3 |
| 167 | #define DTH_TREF_7_8_US 2 |
| 168 | #define DTH_TREF_3_9_US 3 |
| 169 | #define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 170 | #define DTH_TRFC_MASK 7 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 171 | #define DTH_TRFC_75_256M 0 |
| 172 | #define DTH_TRFC_105_512M 1 |
| 173 | #define DTH_TRFC_127_5_1G 2 |
| 174 | #define DTH_TRFC_195_2G 3 |
| 175 | #define DTH_TRFC_327_5_4G 4 |
| 176 | #define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */ |
| 177 | #define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */ |
| 178 | #define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */ |
| 179 | |
| 180 | #define DRAM_CONFIG_LOW 0x90 |
| 181 | #define DCL_InitDram (1<<0) |
| 182 | #define DCL_ExitSelfRef (1<<1) |
| 183 | #define DCL_DramTerm_SHIFT 4 |
| 184 | #define DCL_DramTerm_MASK 3 |
| 185 | #define DCL_DramTerm_No 0 |
| 186 | #define DCL_DramTerm_75_OH 1 |
| 187 | #define DCL_DramTerm_150_OH 2 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 188 | #define DCL_DramTerm_50_OH 3 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 189 | #define DCL_DrvWeak (1<<7) |
| 190 | #define DCL_ParEn (1<<8) |
| 191 | #define DCL_SelfRefRateEn (1<<9) |
| 192 | #define DCL_BurstLength32 (1<<10) |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 193 | #define DCL_Width128 (1<<11) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 194 | #define DCL_X4Dimm_SHIFT 12 |
| 195 | #define DCL_X4Dimm_MASK 0xf |
| 196 | #define DCL_UnBuffDimm (1<<16) |
| 197 | #define DCL_DimmEccEn (1<<19) |
| 198 | |
| 199 | #define DRAM_CONFIG_HIGH 0x94 |
| 200 | #define DCH_MemClkFreq_SHIFT 0 |
| 201 | #define DCH_MemClkFreq_MASK 7 |
| 202 | #define DCH_MemClkFreq_200MHz 0 |
| 203 | #define DCH_MemClkFreq_266MHz 1 |
| 204 | #define DCH_MemClkFreq_333MHz 2 |
| 205 | #define DCH_MemClkFreq_400MHz 3 |
| 206 | #define DCH_MemClkFreqVal (1<<3) |
| 207 | #define DCH_MaxAsyncLat_SHIFT 4 |
| 208 | #define DCH_MaxAsyncLat_MASK 0xf |
| 209 | #define DCH_MaxAsyncLat_BASE 0 |
| 210 | #define DCH_MaxAsyncLat_MIN 0 |
| 211 | #define DCH_MaxAsyncLat_MAX 15 |
| 212 | #define DCH_RDqsEn (1<<12) |
| 213 | #define DCH_DisDramInterface (1<<14) |
| 214 | #define DCH_PowerDownEn (1<<15) |
| 215 | #define DCH_PowerDownMode_SHIFT 16 |
| 216 | #define DCH_PowerDownMode_MASK 1 |
| 217 | #define DCH_PowerDownMode_Channel_CKE 0 |
| 218 | #define DCH_PowerDownMode_ChipSelect_CKE 1 |
| 219 | #define DCH_FourRankSODimm (1<<17) |
| 220 | #define DCH_FourRankRDimm (1<<18) |
| 221 | #define DCH_SlowAccessMode (1<<19) |
| 222 | #define DCH_BankSwizzleMode (1<<22) |
| 223 | #define DCH_DcqBypassMax_SHIFT 24 |
| 224 | #define DCH_DcqBypassMax_MASK 0xf |
| 225 | #define DCH_DcqBypassMax_BASE 0 |
| 226 | #define DCH_DcqBypassMax_MIN 0 |
| 227 | #define DCH_DcqBypassMax_MAX 15 |
| 228 | #define DCH_FourActWindow_SHIFT 28 |
| 229 | #define DCH_FourActWindow_MASK 0xf |
| 230 | #define DCH_FourActWindow_BASE 7 |
| 231 | #define DCH_FourActWindow_MIN 8 |
| 232 | #define DCH_FourActWindow_MAX 20 |
| 233 | |
| 234 | |
| 235 | // for 0x98 index and 0x9c data |
| 236 | #define DRAM_CTRL_ADDI_DATA_OFFSET 0x98 |
| 237 | #define DCAO_DctOffset_SHIFT 0 |
| 238 | #define DCAO_DctOffset_MASK 0x3fffffff |
| 239 | #define DCAO_DctAccessWrite (1<<30) |
| 240 | #define DCAO_DctAccessDone (1<<31) |
| 241 | |
| 242 | #define DRAM_CTRL_ADDI_DATA_PORT 0x9c |
| 243 | |
| 244 | #define DRAM_OUTPUT_DRV_COMP_CTRL 0x00 |
| 245 | #define DODCC_CkeDrvStren_SHIFT 0 |
| 246 | #define DODCC_CkeDrvStren_MASK 3 |
| 247 | #define DODCC_CkeDrvStren_1_0X 0 |
| 248 | #define DODCC_CkeDrvStren_1_25X 1 |
| 249 | #define DODCC_CkeDrvStren_1_5X 2 |
| 250 | #define DODCC_CkeDrvStren_2_0X 3 |
| 251 | #define DODCC_CsOdtDrvStren_SHIFT 4 |
| 252 | #define DODCC_CsOdtDrvStren_MASK 3 |
| 253 | #define DODCC_CsOdtDrvStren_1_0X 0 |
| 254 | #define DODCC_CsOdtDrvStren_1_25X 1 |
| 255 | #define DODCC_CsOdtDrvStren_1_5X 2 |
| 256 | #define DODCC_CsOdtDrvStren_2_0X 3 |
| 257 | #define DODCC_AddrCmdDrvStren_SHIFT 8 |
| 258 | #define DODCC_AddrCmdDrvStren_MASK 3 |
| 259 | #define DODCC_AddrCmdDrvStren_1_0X 0 |
| 260 | #define DODCC_AddrCmdDrvStren_1_25X 1 |
| 261 | #define DODCC_AddrCmdDrvStren_1_5X 2 |
| 262 | #define DODCC_AddrCmdDrvStren_2_0X 3 |
| 263 | #define DODCC_ClkDrvStren_SHIFT 12 |
| 264 | #define DODCC_ClkDrvStren_MASK 3 |
| 265 | #define DODCC_ClkDrvStren_0_75X 0 |
| 266 | #define DODCC_ClkDrvStren_1_0X 1 |
| 267 | #define DODCC_ClkDrvStren_1_25X 2 |
| 268 | #define DODCC_ClkDrvStren_1_5X 3 |
| 269 | #define DODCC_DataDrvStren_SHIFT 16 |
| 270 | #define DODCC_DataDrvStren_MASK 3 |
| 271 | #define DODCC_DataDrvStren_0_75X 0 |
| 272 | #define DODCC_DataDrvStren_1_0X 1 |
| 273 | #define DODCC_DataDrvStren_1_25X 2 |
| 274 | #define DODCC_DataDrvStren_1_5X 3 |
| 275 | #define DODCC_DqsDrvStren_SHIFT 20 |
| 276 | #define DODCC_DqsDrvStren_MASK 3 |
| 277 | #define DODCC_DqsDrvStren_0_75X 0 |
| 278 | #define DODCC_DqsDrvStren_1_0X 1 |
| 279 | #define DODCC_DqsDrvStren_1_25X 2 |
| 280 | #define DODCC_DqsDrvStren_1_5X 3 |
| 281 | #define DODCC_ProcOdt_SHIFT 28 |
| 282 | #define DODCC_ProcOdt_MASK 3 |
| 283 | #define DODCC_ProcOdt_300_OHMS 0 |
| 284 | #define DODCC_ProcOdt_150_OHMS 1 |
| 285 | #define DODCC_ProcOdt_75_OHMS 2 |
| 286 | |
| 287 | #define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01 |
| 288 | #define DWDTCL_WrDatTimeByte0_SHIFT 0 |
| 289 | #define DWDTC_WrDatTimeByte_MASK 0x3f |
| 290 | #define DWDTC_WrDatTimeByte_BASE 0 |
| 291 | #define DWDTC_WrDatTimeByte_MIN 0 |
| 292 | #define DWDTC_WrDatTimeByte_MAX 47 |
| 293 | #define DWDTCL_WrDatTimeByte1_SHIFT 8 |
| 294 | #define DWDTCL_WrDatTimeByte2_SHIFT 16 |
| 295 | #define DWDTCL_WrDatTimeByte3_SHIFT 24 |
| 296 | |
| 297 | #define DRAM_WRITE_DATA_TIMING_CTRL_HIGH 0x02 |
| 298 | #define DWDTCH_WrDatTimeByte4_SHIFT 0 |
| 299 | #define DWDTCH_WrDatTimeByte5_SHIFT 8 |
| 300 | #define DWDTCH_WrDatTimeByte6_SHIFT 16 |
| 301 | #define DWDTCH_WrDatTimeByte7_SHIFT 24 |
| 302 | |
| 303 | #define DRAM_WRITE_DATA_ECC_TIMING_CTRL 0x03 |
| 304 | #define DWDETC_WrChkTime_SHIFT 0 |
| 305 | #define DWDETC_WrChkTime_MASK 0x3f |
| 306 | #define DWDETC_WrChkTime_BASE 0 |
| 307 | #define DWDETC_WrChkTime_MIN 0 |
| 308 | #define DWDETC_WrChkTime_MAX 47 |
| 309 | |
| 310 | #define DRAM_ADDR_TIMING_CTRL 0x04 |
| 311 | #define DATC_CkeFineDelay_SHIFT 0 |
| 312 | #define DATC_CkeFineDelay_MASK 0x1f |
| 313 | #define DATC_CkeFineDelay_BASE 0 |
| 314 | #define DATC_CkeFineDelay_MIN 0 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 315 | #define DATC_CkeFineDelay_MAX 31 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 316 | #define DATC_CkeSetup (1<<5) |
| 317 | #define DATC_CsOdtFineDelay_SHIFT 8 |
| 318 | #define DATC_CsOdtFineDelay_MASK 0x1f |
| 319 | #define DATC_CsOdtFineDelay_BASE 0 |
| 320 | #define DATC_CsOdtFineDelay_MIN 0 |
| 321 | #define DATC_CsOdtFineDelay_MAX 31 |
| 322 | #define DATC_CsOdtSetup (1<<13) |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 323 | #define DATC_AddrCmdFineDelay_SHIFT 16 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 324 | #define DATC_AddrCmdFineDelay_MASK 0x1f |
| 325 | #define DATC_AddrCmdFineDelay_BASE 0 |
| 326 | #define DATC_AddrCmdFineDelay_MIN 0 |
| 327 | #define DATC_AddrCmdFineDelay_MAX 31 |
| 328 | #define DATC_AddrCmdSetup (1<<21) |
| 329 | |
| 330 | #define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05 |
| 331 | #define DRDTCL_RdDqsTimeByte0_SHIFT 0 |
| 332 | #define DRDTC_RdDqsTimeByte_MASK 0x3f |
| 333 | #define DRDTC_RdDqsTimeByte_BASE 0 |
| 334 | #define DRDTC_RdDqsTimeByte_MIN 0 |
| 335 | #define DRDTC_RdDqsTimeByte_MAX 47 |
| 336 | #define DRDTCL_RdDqsTimeByte1_SHIFT 8 |
| 337 | #define DRDTCL_RdDqsTimeByte2_SHIFT 16 |
| 338 | #define DRDTCL_RdDqsTimeByte3_SHIFT 24 |
| 339 | |
| 340 | #define DRAM_READ_DQS_TIMING_CTRL_HIGH 0x06 |
| 341 | #define DRDTCH_RdDqsTimeByte4_SHIFT 0 |
| 342 | #define DRDTCH_RdDqsTimeByte5_SHIFT 8 |
| 343 | #define DRDTCH_RdDqsTimeByte6_SHIFT 16 |
| 344 | #define DRDTCH_RdDqsTimeByte7_SHIFT 24 |
| 345 | |
| 346 | #define DRAM_READ_DQS_ECC_TIMING_CTRL 0x07 |
| 347 | #define DRDETC_RdDqsTimeCheck_SHIFT 0 |
| 348 | #define DRDETC_RdDqsTimeCheck_MASK 0x3f |
| 349 | #define DRDETC_RdDqsTimeCheck_BASE 0 |
| 350 | #define DRDETC_RdDqsTimeCheck_MIN 0 |
| 351 | #define DRDETC_RdDqsTimeCheck_MAX 47 |
| 352 | |
| 353 | #define DRAM_DQS_RECV_ENABLE_TIME0 0x10 |
| 354 | #define DDRET_DqsRcvEnDelay_SHIFT 0 |
| 355 | #define DDRET_DqsRcvEnDelay_MASK 0xff |
| 356 | #define DDRET_DqsRcvEnDelay_BASE 0 |
| 357 | #define DDRET_DqsRcvEnDelay_MIN 0 |
| 358 | #define DDRET_DqsRcvEnDelay_MAX 0xae /* unit is 50ps */ |
| 359 | |
| 360 | #define DRAM_DQS_RECV_ENABLE_TIME1 0x13 |
| 361 | #define DRAM_DQS_RECV_ENABLE_TIME2 0x16 |
| 362 | #define DRAM_DQS_RECV_ENABLE_TIME3 0x19 |
| 363 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 364 | /* there are index 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 365 | that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, 0x13, 0x16, 0x19 |
| 366 | */ |
| 367 | #define DRAM_CTRL_MISC 0xa0 |
| 368 | #define DCM_MemClrStatus (1<<0) |
| 369 | #define DCM_DisableJitter (1<<1) |
| 370 | #define DCM_RdWrQByp_SHIFT 2 |
| 371 | #define DCM_RdWrQByp_MASK 3 |
| 372 | #define DCM_RdWrQByp_2 0 |
| 373 | #define DCM_RdWrQByp_4 1 |
| 374 | #define DCM_RdWrQByp_8 2 |
| 375 | #define DCM_RdWrQByp_16 3 |
| 376 | #define DCM_Mode64BitMux (1<<4) |
| 377 | #define DCM_DCC_EN (1<<5) |
| 378 | #define DCM_ILD_lmt_SHIFT 6 |
| 379 | #define DCM_ILD_lmt_MASK 7 |
| 380 | #define DCM_ILD_lmt_0 0 |
| 381 | #define DCM_ILD_lmt_4 1 |
| 382 | #define DCM_ILD_lmt_8 2 |
| 383 | #define DCM_ILD_lmt_16 3 |
| 384 | #define DCM_ILD_lmt_32 4 |
| 385 | #define DCM_ILD_lmt_64 5 |
| 386 | #define DCM_ILD_lmt_128 6 |
| 387 | #define DCM_ILD_lmt_256 7 |
| 388 | #define DCM_DramEnabled (1<<9) |
| 389 | #define DCM_MemClkDis_SHIFT 24 /* Channel B */ |
| 390 | #define DCM_MemClkDis3 (1 << 26) |
| 391 | #define DCM_MemClkDis2 (1 << 27) |
| 392 | #define DCM_MemClkDis1 (1 << 28) |
| 393 | #define DCM_MemClkDis0 (1 << 29) |
| 394 | |
| 395 | |
| 396 | /* Function 3 */ |
| 397 | #define MCA_NB_CONFIG 0x44 |
| 398 | #define MNC_ECC_EN (1 << 22) |
| 399 | #define MNC_CHIPKILL_EN (1 << 23) |
| 400 | |
| 401 | #define SCRUB_CONTROL 0x58 |
| 402 | #define SCRUB_NONE 0 |
| 403 | #define SCRUB_40ns 1 |
| 404 | #define SCRUB_80ns 2 |
| 405 | #define SCRUB_160ns 3 |
| 406 | #define SCRUB_320ns 4 |
| 407 | #define SCRUB_640ns 5 |
| 408 | #define SCRUB_1_28us 6 |
| 409 | #define SCRUB_2_56us 7 |
| 410 | #define SCRUB_5_12us 8 |
| 411 | #define SCRUB_10_2us 9 |
| 412 | #define SCRUB_20_5us 10 |
| 413 | #define SCRUB_41_0us 11 |
| 414 | #define SCRUB_81_9us 12 |
| 415 | #define SCRUB_163_8us 13 |
| 416 | #define SCRUB_327_7us 14 |
| 417 | #define SCRUB_655_4us 15 |
| 418 | #define SCRUB_1_31ms 16 |
| 419 | #define SCRUB_2_62ms 17 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 420 | #define SCRUB_5_24ms 18 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 421 | #define SCRUB_10_49ms 19 |
| 422 | #define SCRUB_20_97ms 20 |
| 423 | #define SCRUB_42ms 21 |
| 424 | #define SCRUB_84ms 22 |
| 425 | #define SC_DRAM_SCRUB_RATE_SHFIT 0 |
| 426 | #define SC_DRAM_SCRUB_RATE_MASK 0x1f |
| 427 | #define SC_L2_SCRUB_RATE_SHIFT 8 |
| 428 | #define SC_L2_SCRUB_RATE_MASK 0x1f |
| 429 | #define SC_L1D_SCRUB_RATE_SHIFT 16 |
| 430 | #define SC_L1D_SCRUB_RATE_MASK 0x1f |
| 431 | |
| 432 | #define SCRUB_ADDR_LOW 0x5C |
| 433 | |
| 434 | #define SCRUB_ADDR_HIGH 0x60 |
| 435 | |
| 436 | #define NORTHBRIDGE_CAP 0xE8 |
| 437 | #define NBCAP_128Bit (1 << 0) |
| 438 | #define NBCAP_MP (1 << 1) |
| 439 | #define NBCAP_BIG_MP (1 << 2) |
| 440 | #define NBCAP_ECC (1 << 3) |
| 441 | #define NBCAP_CHIPKILL_ECC (1 << 4) |
| 442 | #define NBCAP_MEMCLK_SHIFT 5 |
| 443 | #define NBCAP_MEMCLK_MASK 3 |
| 444 | #define NBCAP_MEMCLK_200MHZ 3 |
| 445 | #define NBCAP_MEMCLK_266MHZ 2 |
| 446 | #define NBCAP_MEMCLK_333MHZ 1 |
| 447 | #define NBCAP_MEMCLK_NOLIMIT 0 |
| 448 | #define NBCAP_MEMCTRL (1 << 8) |
| 449 | #define NBCAP_HtcCap (1<<10) |
| 450 | #define NBCAP_CmpCap_SHIFT 12 |
| 451 | #define NBCAP_CmpCap_MASK 3 |
| 452 | |
| 453 | |
| 454 | #define LinkConnected (1 << 0) |
| 455 | #define InitComplete (1 << 1) |
| 456 | #define NonCoherent (1 << 2) |
| 457 | #define ConnectionPending (1 << 4) |
| 458 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 459 | #include "raminit.h" |
| 460 | //struct definitions |
| 461 | |
| 462 | struct dimm_size { |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 463 | uint8_t per_rank; // it is rows + col + bank_lines + data lines */ |
| 464 | uint8_t rows; |
| 465 | uint8_t col; |
| 466 | uint8_t bank; //1, 2, 3 mean 2, 4, 8 |
| 467 | uint8_t rank; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 468 | } __attribute__((packed)); |
| 469 | |
| 470 | struct mem_info { // pernode |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 471 | uint32_t dimm_mask; |
| 472 | struct dimm_size sz[DIMM_SOCKETS]; |
| 473 | uint32_t x4_mask; |
| 474 | uint32_t x16_mask; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 475 | uint32_t single_rank_mask; |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 476 | uint32_t page_1k_mask; |
| 477 | // uint32_t ecc_mask; |
| 478 | // uint32_t registered_mask; |
| 479 | uint8_t is_opteron; |
| 480 | uint8_t is_registered; |
| 481 | uint8_t is_ecc; |
| 482 | uint8_t is_Width128; |
Marc Jones | b5623d1 | 2008-09-29 18:09:51 +0000 | [diff] [blame] | 483 | uint8_t is_64MuxMode; |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 484 | uint8_t memclk_set; // we need to use this to retrieve the mem param |
Marc Jones | b5623d1 | 2008-09-29 18:09:51 +0000 | [diff] [blame] | 485 | uint8_t rsv[2]; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 486 | } __attribute__((packed)); |
| 487 | |
| 488 | struct link_pair_st { |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 489 | device_t udev; |
| 490 | uint32_t upos; |
| 491 | uint32_t uoffs; |
| 492 | device_t dev; |
| 493 | uint32_t pos; |
| 494 | uint32_t offs; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 495 | |
| 496 | } __attribute__((packed)); |
| 497 | |
| 498 | struct sys_info { |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 499 | uint8_t ctrl_present[NODE_NUMS]; |
| 500 | struct mem_info meminfo[NODE_NUMS]; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 501 | struct mem_controller ctrl[NODE_NUMS]; |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 502 | uint8_t mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 503 | uint32_t tom_k; |
| 504 | uint32_t tom2_k; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 505 | |
| 506 | uint32_t mem_base[NODE_NUMS]; |
| 507 | uint32_t cs_base[NODE_NUMS*8]; //8 cs_idx |
| 508 | uint32_t hole_reg[NODE_NUMS]; // can we spare it to one, and put ctrl idx in it |
| 509 | |
| 510 | uint8_t dqs_delay_a[NODE_NUMS*2*2*9]; //8 node channel 2, direction 2 , bytelane *9 |
| 511 | uint8_t dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8 |
| 512 | uint32_t nodes; |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 513 | struct link_pair_st link_pair[16];// enough? only in_conherent |
| 514 | uint32_t link_pair_num; |
| 515 | uint32_t ht_c_num; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 516 | uint32_t sbdn; |
| 517 | uint32_t sblk; |
| 518 | uint32_t sbbusn; |
| 519 | } __attribute__((packed)); |
| 520 | |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 521 | #ifdef __PRE_RAM__ |
Aaron Durbin | 0dc7354 | 2015-07-16 16:07:02 -0500 | [diff] [blame] | 522 | #include <arch/early_variables.h> |
| 523 | struct sys_info sysinfo_car CAR_GLOBAL; |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 524 | #endif |
| 525 | |
Stefan Reinauer | 23a3e79 | 2010-03-30 22:03:10 +0000 | [diff] [blame] | 526 | #include <reset.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 527 | |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 528 | #if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \ |
| 529 | ((CONFIG_MEM_TRAIN_SEQ == 1) && !defined(__PRE_RAM__)) |
Stefan Reinauer | eea66b7 | 2010-04-07 15:32:52 +0000 | [diff] [blame] | 530 | static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 531 | { |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 532 | |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 533 | int i; |
| 534 | uint32_t mask = 0; |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 535 | unsigned needs_reset = 0; |
| 536 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 537 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 538 | if(sysinfo->nodes == 1) return; // in case only one cpu installed |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 539 | |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 540 | for(i=1; i<sysinfo->nodes; i++) { |
| 541 | /* Skip everything if I don't have any memory on this controller */ |
| 542 | if(sysinfo->mem_trained[i]==0x00) continue; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 543 | |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 544 | mask |= (1<<i); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 545 | |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 546 | } |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 547 | |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 548 | i = 1; |
| 549 | while(1) { |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 550 | if(mask & (1<<i)) { |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 551 | if((sysinfo->mem_trained[i])!=0x80) { |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 552 | mask &= ~(1<<i); |
| 553 | } |
| 554 | } |
| 555 | |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 556 | if(!mask) break; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 557 | |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 558 | #if 0 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 559 | /* cpu_relax */ |
| 560 | __asm__ __volatile__("rep;nop": : :"memory"); |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 561 | #endif |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 562 | |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 563 | i++; |
| 564 | i%=sysinfo->nodes; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 565 | } |
| 566 | |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 567 | for(i=0; i<sysinfo->nodes; i++) { |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 568 | printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); |
Myles Watson | d61ada6 | 2008-10-02 19:20:22 +0000 | [diff] [blame] | 569 | switch(sysinfo->mem_trained[i]) { |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 570 | case 0: //don't need train |
| 571 | case 1: //trained |
| 572 | break; |
| 573 | case 0x81: //recv1: fail |
| 574 | case 0x82: //Pos :fail |
| 575 | case 0x83: //recv2: fail |
| 576 | needs_reset = 1; |
| 577 | break; |
| 578 | } |
| 579 | } |
| 580 | if(needs_reset) { |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 581 | printk(BIOS_DEBUG, "mem trained failed\n"); |
Myles Watson | 1d6d45e | 2009-11-06 17:02:51 +0000 | [diff] [blame] | 582 | #ifdef __PRE_RAM__ |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 583 | soft_reset(); |
| 584 | #else |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 585 | hard_reset(); |
| 586 | #endif |
| 587 | } |
| 588 | |
| 589 | } |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 590 | #endif |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 591 | |
| 592 | #endif /* AMDK8_F_H */ |