Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Timothy Pearson | 586d6e2 | 2015-02-16 14:57:06 -0600 | [diff] [blame] | 4 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 5 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef AMDFAM10_H |
| 18 | |
| 19 | #define AMDFAM10_H |
| 20 | /* Definitions of various FAM10 registers */ |
| 21 | /* Function 0 */ |
| 22 | #define HT_TRANSACTION_CONTROL 0x68 |
| 23 | #define HTTC_DIS_RD_B_P (1 << 0) |
| 24 | #define HTTC_DIS_RD_DW_P (1 << 1) |
| 25 | #define HTTC_DIS_WR_B_P (1 << 2) |
| 26 | #define HTTC_DIS_WR_DW_P (1 << 3) |
| 27 | #define HTTC_DIS_MTS (1 << 4) |
| 28 | #define HTTC_CPU1_EN (1 << 5) |
| 29 | #define HTTC_CPU_REQ_PASS_PW (1 << 6) |
| 30 | #define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) |
| 31 | #define HTTC_DIS_P_MEM_C (1 << 8) |
| 32 | #define HTTC_DIS_RMT_MEM_C (1 << 9) |
| 33 | #define HTTC_DIS_FILL_P (1 << 10) |
| 34 | #define HTTC_RSP_PASS_PW (1 << 11) |
| 35 | #define HTTC_BUF_REL_PRI_SHIFT 13 |
| 36 | #define HTTC_BUF_REL_PRI_MASK 3 |
| 37 | #define HTTC_BUF_REL_PRI_64 0 |
| 38 | #define HTTC_BUF_REL_PRI_16 1 |
| 39 | #define HTTC_BUF_REL_PRI_8 2 |
| 40 | #define HTTC_BUF_REL_PRI_2 3 |
| 41 | #define HTTC_LIMIT_CLDT_CFG (1 << 15) |
| 42 | #define HTTC_LINT_EN (1 << 16) |
| 43 | #define HTTC_APIC_EXT_BRD_CST (1 << 17) |
| 44 | #define HTTC_APIC_EXT_ID (1 << 18) |
| 45 | #define HTTC_APIC_EXT_SPUR (1 << 19) |
| 46 | #define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) |
| 47 | #define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 |
| 48 | #define HTTC_DS_NP_REQ_LIMIT_MASK 3 |
| 49 | #define HTTC_DS_NP_REQ_LIMIT_NONE 0 |
| 50 | #define HTTC_DS_NP_REQ_LIMIT_1 1 |
| 51 | #define HTTC_DS_NP_REQ_LIMIT_4 2 |
| 52 | #define HTTC_DS_NP_REQ_LIMIT_8 3 |
| 53 | |
| 54 | |
| 55 | /* Function 1 */ |
| 56 | #define PCI_IO_BASE0 0xc0 |
| 57 | #define PCI_IO_BASE1 0xc8 |
| 58 | #define PCI_IO_BASE2 0xd0 |
| 59 | #define PCI_IO_BASE3 0xd8 |
| 60 | #define PCI_IO_BASE_VGA_EN (1 << 4) |
| 61 | #define PCI_IO_BASE_NO_ISA (1 << 5) |
| 62 | |
| 63 | /* Function 2 */ |
| 64 | // 0x1xx is for DCT1 |
| 65 | #define DRAM_CSBASE 0x40 |
| 66 | #define DRAM_CSMASK 0x60 |
| 67 | #define DRAM_BANK_ADDR_MAP 0x80 |
| 68 | |
| 69 | #define DRAM_CTRL 0x78 |
| 70 | #define DC_RdPtrInit_SHIFT 0 |
| 71 | #define DC_RdPrtInit_MASK 0xf |
| 72 | #define DC_Twrrd3_2_SHIFT 8 /*DDR3 */ |
| 73 | #define DC_Twrrd3_2_MASK 3 |
| 74 | #define DC_Twrwr3_2_SHIFT 10 /*DDR3 */ |
| 75 | #define DC_Twrwr3_2_MASK 3 |
| 76 | #define DC_Trdrd3_2_SHIFT 12 /*DDR3 */ |
| 77 | #define DC_Trdrd3_2_MASK 3 |
| 78 | #define DC_AltVidC3MemClkTriEn (1<<16) |
| 79 | #define DC_DqsRcvEnTrain (1<<18) |
| 80 | #define DC_MaxRdLatency_SHIFT 22 |
| 81 | #define DC_MaxRdLatency_MASK 0x3ff |
| 82 | |
| 83 | #define DRAM_INIT 0x7c |
| 84 | #define DI_MrsAddress_SHIFT 0 |
| 85 | #define DI_MrsAddress_MASK 0xffff |
| 86 | #define DI_MrsBank_SHIFT 16 |
| 87 | #define DI_MrsBank_MASK 7 |
| 88 | #define DI_MrsChipSel_SHIFT 20 |
| 89 | #define DI_MrsChipSel_MASK 7 |
| 90 | #define DI_SendRchgAll (1<<24) |
| 91 | #define DI_SendAutoRefresh (1<<25) |
| 92 | #define DI_SendMrsCmd (1<<26) |
| 93 | #define DI_DeassertMemRstX (1<<27) |
| 94 | #define DI_AssertCke (1<<28) |
| 95 | #define DI_SendZQCmd (1<<29) /*DDR3 */ |
| 96 | #define DI_EnMrsCmd (1<<30) |
| 97 | #define DI_EnDramInit (1<<31) |
| 98 | |
| 99 | #define DRAM_MRS 0x84 |
| 100 | #define DM_BurstCtrl_SHIFT 0 |
| 101 | #define DM_BurstCtrl_MASK 3 |
| 102 | #define DM_DrvImpCtrl_SHIFT 2 /* DDR3 */ |
| 103 | #define DM_DrvImpCtrl_MASK 3 |
| 104 | #define DM_Twr_SHIFT 4 /* DDR3 */ |
| 105 | #define DM_Twr_MASK 7 |
| 106 | #define DM_Twr_BASE 4 |
| 107 | #define DM_Twr_MIN 5 |
| 108 | #define DM_Twr_MAX 12 |
| 109 | #define DM_DramTerm_SHIFT 7 /*DDR3 */ |
| 110 | #define DM_DramTerm_MASK 7 |
| 111 | #define DM_DramTermDyn_SHIFT 10 /* DDR3 */ |
| 112 | #define DM_DramTermDyn_MASK 3 |
| 113 | #define DM_Ooff (1<<13) |
| 114 | #define DM_ASR (1<<18) |
| 115 | #define DM_SRT (1<<19) |
| 116 | #define DM_Tcwl_SHIFT 20 |
| 117 | #define DM_Tcwl_MASK 7 |
| 118 | #define DM_PchgPDModeSel (1<<23) /* DDR3 */ |
| 119 | #define DM_MPrLoc_SHIFT 24 /* DDR3 */ |
| 120 | #define DM_MPrLoc_MASK 3 |
| 121 | #define DM_MprEn (1<<26) /* DDR3 */ |
| 122 | |
| 123 | #define DRAM_TIMING_LOW 0x88 |
| 124 | #define DTL_TCL_SHIFT 0 |
| 125 | #define DTL_TCL_MASK 0xf |
| 126 | #define DTL_TCL_BASE 1 /* DDR3 =4 */ |
| 127 | #define DTL_TCL_MIN 3 /* DDR3 =4 */ |
| 128 | #define DTL_TCL_MAX 6 /* DDR3 =12 */ |
| 129 | #define DTL_TRCD_SHIFT 4 |
| 130 | #define DTL_TRCD_MASK 3 /* DDR3 =7 */ |
| 131 | #define DTL_TRCD_BASE 3 /* DDR3 =5 */ |
| 132 | #define DTL_TRCD_MIN 3 /* DDR3 =5 */ |
| 133 | #define DTL_TRCD_MAX 6 /* DDR3 =12 */ |
| 134 | #define DTL_TRP_SHIFT 8 /* DDR3 =7 */ |
| 135 | #define DTL_TRP_MASK 3 /* DDR3 =7 */ |
| 136 | #define DTL_TRP_BASE 3 /* DDR3 =5 */ |
| 137 | #define DTL_TRP_MIN 3 /* DDR3 =5 */ |
| 138 | #define DTL_TRP_MAX 6 /* DDR3 =12 */ |
| 139 | #define DTL_TRTP_SHIFT 11 /*DDR3 =10 */ |
| 140 | #define DTL_TRTP_MASK 1 /*DDR3 =3 */ |
| 141 | #define DTL_TRTP_BASE 2 /* DDR3 =4 */ |
| 142 | #define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/ /* DDR3 =4 for 32bytes or 64bytes */ |
| 143 | #define DTL_TRTP_MAX 3 /* 5 for 64 bytes */ /* DDR3 =7 for 32Bytes or 64bytes */ |
| 144 | #define DTL_TRAS_SHIFT 12 |
| 145 | #define DTL_TRAS_MASK 0xf |
| 146 | #define DTL_TRAS_BASE 3 /* DDR3 =15 */ |
| 147 | #define DTL_TRAS_MIN 5 /* DDR3 =15 */ |
| 148 | #define DTL_TRAS_MAX 18 /*DDR3 =30 */ |
| 149 | #define DTL_TRC_SHIFT 16 |
| 150 | #define DTL_TRC_MASK 0xf /* DDR3 =0x1f */ |
| 151 | #define DTL_TRC_BASE 11 |
| 152 | #define DTL_TRC_MIN 11 |
| 153 | #define DTL_TRC_MAX 26 /* DDR3 =43 */ |
| 154 | #define DTL_TWR_SHIFT 20 /* only for DDR2, DDR3's is on DC */ |
| 155 | #define DTL_TWR_MASK 3 |
| 156 | #define DTL_TWR_BASE 3 |
| 157 | #define DTL_TWR_MIN 3 |
| 158 | #define DTL_TWR_MAX 6 |
| 159 | #define DTL_TRRD_SHIFT 22 |
| 160 | #define DTL_TRRD_MASK 3 |
| 161 | #define DTL_TRRD_BASE 2 /* DDR3 =4 */ |
| 162 | #define DTL_TRRD_MIN 2 /* DDR3 =4 */ |
| 163 | #define DTL_TRRD_MAX 5 /* DDR3 =7 */ |
| 164 | #define DTL_MemClkDis_SHIFT 24 /* Channel A */ |
| 165 | #define DTL_MemClkDis3 (1 << 26) |
| 166 | #define DTL_MemClkDis2 (1 << 27) |
| 167 | #define DTL_MemClkDis1 (1 << 28) |
| 168 | #define DTL_MemClkDis0 (1 << 29) |
| 169 | /* DTL_MemClkDis for m2 and s1g1 is different */ |
| 170 | |
| 171 | #define DRAM_TIMING_HIGH 0x8c |
| 172 | #define DTH_TRWTWB_SHIFT 0 |
| 173 | #define DTH_TRWTWB_MASK 3 |
| 174 | #define DTH_TRWTWB_BASE 3 /* DDR3 =4 */ |
| 175 | #define DTH_TRWTWB_MIN 3 /* DDR3 =5 */ |
| 176 | #define DTH_TRWTWB_MAX 10 /* DDR3 =11 */ |
| 177 | #define DTH_TRWTTO_SHIFT 4 |
| 178 | #define DTH_TRWTTO_MASK 7 |
| 179 | #define DTH_TRWTTO_BASE 2 /* DDR3 =3 */ |
| 180 | #define DTH_TRWTTO_MIN 2 /* DDR3 =3 */ |
| 181 | #define DTH_TRWTTO_MAX 9 /* DDR3 =10 */ |
| 182 | #define DTH_TWTR_SHIFT 8 |
| 183 | #define DTH_TWTR_MASK 3 |
| 184 | #define DTH_TWTR_BASE 0 /* DDR3 =4 */ |
| 185 | #define DTH_TWTR_MIN 1 /* DDR3 =4 */ |
| 186 | #define DTH_TWTR_MAX 3 /* DDR3 =7 */ |
| 187 | #define DTH_TWRRD_SHIFT 10 |
| 188 | #define DTH_TWRRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ |
| 189 | #define DTH_TWRRD_BASE 0 /* DDR3 =0 */ |
| 190 | #define DTH_TWRRD_MIN 0 /* DDR3 =2 */ |
| 191 | #define DTH_TWRRD_MAX 3 /* DDR3 =12 */ |
| 192 | #define DTH_TWRWR_SHIFT 12 |
| 193 | #define DTH_TWRWR_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ |
| 194 | #define DTH_TWRWR_BASE 1 |
| 195 | #define DTH_TWRWR_MIN 1 /* DDR3 =3 */ |
| 196 | #define DTH_TWRWR_MAX 3 /* DDR3 =12 */ |
| 197 | #define DTH_TRDRD_SHIFT 14 |
| 198 | #define DTH_TRDRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ |
| 199 | #define DTH_TRDRD_BASE 2 |
| 200 | #define DTH_TRDRD_MIN 2 |
| 201 | #define DTH_TRDRD_MAX 5 /* DDR3 =10 */ |
| 202 | #define DTH_TREF_SHIFT 16 |
| 203 | #define DTH_TREF_MASK 3 |
| 204 | #define DTH_TREF_7_8_US 2 |
| 205 | #define DTH_TREF_3_9_US 3 |
| 206 | #define DTH_DisAutoRefresh (1<<18) |
| 207 | #define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */ |
| 208 | #define DTH_TRFC_MASK 7 |
| 209 | #define DTH_TRFC_75_256M 0 |
| 210 | #define DTH_TRFC_105_512M 1 |
| 211 | #define DTH_TRFC_127_5_1G 2 |
| 212 | #define DTH_TRFC_195_2G 3 |
| 213 | #define DTH_TRFC_327_5_4G 4 |
| 214 | #if 0 |
| 215 | //DDR3 |
| 216 | #define DTH_TRFC_90_512M 1 |
| 217 | #define DTH_TRFC_110_5_1G 2 |
| 218 | #define DTH_TRFC_160_2G 3 |
| 219 | #define DTH_TRFC_300_4G 4 |
| 220 | #define DTH_TRFC_UNDEFINED_8G 5 |
| 221 | #endif |
| 222 | #define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */ |
| 223 | #define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */ |
| 224 | #define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */ |
| 225 | |
| 226 | #define DRAM_CONFIG_LOW 0x90 |
| 227 | #define DCL_InitDram (1<<0) |
| 228 | #define DCL_ExitSelfRef (1<<1) |
| 229 | #define DCL_PllLockTime_SHIFT 2 |
| 230 | #define DCL_PllLockTime_MASK 3 |
| 231 | #define DCL_PllLockTime_15US 0 |
| 232 | #define DCL_PllLockTime_6US 1 |
| 233 | #define DCL_DramTerm_SHIFT 4 |
| 234 | #define DCL_DramTerm_MASK 3 |
| 235 | #define DCL_DramTerm_No 0 |
| 236 | #define DCL_DramTerm_75_OH 1 |
| 237 | #define DCL_DramTerm_150_OH 2 |
| 238 | #define DCL_DramTerm_50_OH 3 |
| 239 | #define DCL_DisDqsBar (1<<6) /* only for DDR2 */ |
| 240 | #define DCL_DramDrvWeak (1<<7) /* only for DDR2 */ |
| 241 | #define DCL_ParEn (1<<8) |
| 242 | #define DCL_SelfRefRateEn (1<<9) /* only for DDR2 */ |
| 243 | #define DCL_BurstLength32 (1<<10) /* only for DDR3 */ |
| 244 | #define DCL_Width128 (1<<11) |
| 245 | #define DCL_X4Dimm_SHIFT 12 |
| 246 | #define DCL_X4Dimm_MASK 0xf |
| 247 | #define DCL_UnBuffDimm (1<<16) |
| 248 | #define DCL_EnPhyDqsRcvEnTr (1<<18) |
| 249 | #define DCL_DimmEccEn (1<<19) |
| 250 | #define DCL_DynPageCloseEn (1<<20) |
| 251 | #define DCL_IdleCycInit_SHIFT 21 |
| 252 | #define DCL_IdleCycInit_MASK 3 |
| 253 | #define DCL_IdleCycInit_16CLK 0 |
| 254 | #define DCL_IdleCycInit_32CLK 1 |
| 255 | #define DCL_IdleCycInit_64CLK 2 |
| 256 | #define DCL_IdleCycInit_96CLK 3 |
| 257 | #define DCL_ForceAutoPchg (1<<23) |
| 258 | |
| 259 | #define DRAM_CONFIG_HIGH 0x94 |
| 260 | #define DCH_MemClkFreq_SHIFT 0 |
| 261 | #define DCH_MemClkFreq_MASK 7 |
| 262 | #define DCH_MemClkFreq_200MHz 0 /* DDR2 */ |
| 263 | #define DCH_MemClkFreq_266MHz 1 /* DDR2 */ |
| 264 | #define DCH_MemClkFreq_333MHz 2 /* DDR2 */ |
| 265 | #define DCH_MemClkFreq_400MHz 3 /* DDR2 and DDR 3*/ |
| 266 | #define DCH_MemClkFreq_533MHz 4 /* DDR 3 */ |
| 267 | #define DCH_MemClkFreq_667MHz 5 /* DDR 3 */ |
| 268 | #define DCH_MemClkFreq_800MHz 6 /* DDR 3 */ |
| 269 | #define DCH_MemClkFreqVal (1<<3) |
| 270 | #define DCH_Ddr3Mode (1<<8) |
| 271 | #define DCH_LegacyBiosMode (1<<9) |
| 272 | #define DCH_ZqcsInterval_SHIFT 10 |
| 273 | #define DCH_ZqcsInterval_MASK 3 |
| 274 | #define DCH_ZqcsInterval_DIS 0 |
| 275 | #define DCH_ZqcsInterval_64MS 1 |
| 276 | #define DCH_ZqcsInterval_128MS 2 |
| 277 | #define DCH_ZqcsInterval_256MS 3 |
| 278 | #define DCH_RDqsEn (1<<12) /* only for DDR2 */ |
| 279 | #define DCH_DisSimulRdWr (1<<13) |
| 280 | #define DCH_DisDramInterface (1<<14) |
| 281 | #define DCH_PowerDownEn (1<<15) |
| 282 | #define DCH_PowerDownMode_SHIFT 16 |
| 283 | #define DCH_PowerDownMode_MASK 1 |
| 284 | #define DCH_PowerDownMode_Channel_CKE 0 |
| 285 | #define DCH_PowerDownMode_ChipSelect_CKE 1 |
| 286 | #define DCH_FourRankSODimm (1<<17) |
| 287 | #define DCH_FourRankRDimm (1<<18) |
| 288 | #define DCH_SlowAccessMode (1<<20) |
| 289 | #define DCH_BankSwizzleMode (1<<22) |
| 290 | #define DCH_DcqBypassMax_SHIFT 24 |
| 291 | #define DCH_DcqBypassMax_MASK 0xf |
| 292 | #define DCH_DcqBypassMax_BASE 0 |
| 293 | #define DCH_DcqBypassMax_MIN 0 |
| 294 | #define DCH_DcqBypassMax_MAX 15 |
| 295 | #define DCH_FourActWindow_SHIFT 28 |
| 296 | #define DCH_FourActWindow_MASK 0xf |
| 297 | #define DCH_FourActWindow_BASE 7 /* DDR3 15 */ |
| 298 | #define DCH_FourActWindow_MIN 8 /* DDR3 16 */ |
| 299 | #define DCH_FourActWindow_MAX 20 /* DDR3 30 */ |
| 300 | |
| 301 | |
| 302 | // for 0x98 index and 0x9c data for DCT0 |
| 303 | // for 0x198 index and 0x19c data for DCT1 |
| 304 | // even at ganged mode, 0x198/0x19c will be used for channnel B |
| 305 | |
| 306 | #define DRAM_CTRL_ADDI_DATA_OFFSET 0x98 |
| 307 | #define DCAO_DctOffset_SHIFT 0 |
| 308 | #define DCAO_DctOffset_MASK 0x3fffffff |
| 309 | #define DCAO_DctAccessWrite (1<<30) |
| 310 | #define DCAO_DctAccessDone (1<<31) |
| 311 | |
| 312 | #define DRAM_CTRL_ADDI_DATA_PORT 0x9c |
| 313 | |
| 314 | #define DRAM_OUTPUT_DRV_COMP_CTRL 0x00 |
| 315 | #define DODCC_CkeDrvStren_SHIFT 0 |
| 316 | #define DODCC_CkeDrvStren_MASK 3 |
| 317 | #define DODCC_CkeDrvStren_1_0X 0 |
| 318 | #define DODCC_CkeDrvStren_1_25X 1 |
| 319 | #define DODCC_CkeDrvStren_1_5X 2 |
| 320 | #define DODCC_CkeDrvStren_2_0X 3 |
| 321 | #define DODCC_CsOdtDrvStren_SHIFT 4 |
| 322 | #define DODCC_CsOdtDrvStren_MASK 3 |
| 323 | #define DODCC_CsOdtDrvStren_1_0X 0 |
| 324 | #define DODCC_CsOdtDrvStren_1_25X 1 |
| 325 | #define DODCC_CsOdtDrvStren_1_5X 2 |
| 326 | #define DODCC_CsOdtDrvStren_2_0X 3 |
| 327 | #define DODCC_AddrCmdDrvStren_SHIFT 8 |
| 328 | #define DODCC_AddrCmdDrvStren_MASK 3 |
| 329 | #define DODCC_AddrCmdDrvStren_1_0X 0 |
| 330 | #define DODCC_AddrCmdDrvStren_1_25X 1 |
| 331 | #define DODCC_AddrCmdDrvStren_1_5X 2 |
| 332 | #define DODCC_AddrCmdDrvStren_2_0X 3 |
| 333 | #define DODCC_ClkDrvStren_SHIFT 12 |
| 334 | #define DODCC_ClkDrvStren_MASK 3 |
| 335 | #define DODCC_ClkDrvStren_0_75X 0 |
| 336 | #define DODCC_ClkDrvStren_1_0X 1 |
| 337 | #define DODCC_ClkDrvStren_1_25X 2 |
| 338 | #define DODCC_ClkDrvStren_1_5X 3 |
| 339 | #define DODCC_DataDrvStren_SHIFT 16 |
| 340 | #define DODCC_DataDrvStren_MASK 3 |
| 341 | #define DODCC_DataDrvStren_0_75X 0 |
| 342 | #define DODCC_DataDrvStren_1_0X 1 |
| 343 | #define DODCC_DataDrvStren_1_25X 2 |
| 344 | #define DODCC_DataDrvStren_1_5X 3 |
| 345 | #define DODCC_DqsDrvStren_SHIFT 20 |
| 346 | #define DODCC_DqsDrvStren_MASK 3 |
| 347 | #define DODCC_DqsDrvStren_0_75X 0 |
| 348 | #define DODCC_DqsDrvStren_1_0X 1 |
| 349 | #define DODCC_DqsDrvStren_1_25X 2 |
| 350 | #define DODCC_DqsDrvStren_1_5X 3 |
| 351 | #define DODCC_ProcOdt_SHIFT 28 |
| 352 | #define DODCC_ProcOdt_MASK 3 |
| 353 | #define DODCC_ProcOdt_300_OHMS 0 |
| 354 | #define DODCC_ProcOdt_150_OHMS 1 |
| 355 | #define DODCC_ProcOdt_75_OHMS 2 |
| 356 | #if 0 |
| 357 | //DDR3 |
| 358 | #define DODCC_ProcOdt_240_OHMS 0 |
| 359 | #define DODCC_ProcOdt_120_OHMS 1 |
| 360 | #define DODCC_ProcOdt_60_OHMS 2 |
| 361 | #endif |
| 362 | |
| 363 | /* |
| 364 | for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of all DIMMs |
| 365 | for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of DIMM0 |
| 366 | F2x[1,0]9C_x[102:101], [103], [106:105], [107] controll timing of DIMM1 |
| 367 | So Socket F with Four Logical DIMM will only support DDR2 800 ? |
| 368 | */ |
| 369 | /* there are index +100 ===> for DIMM1 |
| 370 | that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 |
| 371 | */ |
| 372 | //02/15/2006 18:37 |
| 373 | #define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01 |
| 374 | #define DWDTC_WrDatFineDlyByte0_SHIFT 0 |
| 375 | #define DWDTC_WrDatFineDlyByte_MASK 0x1f |
| 376 | #define DWDTC_WrDatFineDlyByte_BASE 0 |
| 377 | #define DWDTC_WrDatFineDlyByte_MIN 0 |
| 378 | #define DWDTC_WrDatFineDlyByte_MAX 31 // 1/64 MEMCLK |
| 379 | #define DWDTC_WrDatGrossDlyByte0_SHIFT 5 |
| 380 | #define DWDTC_WrDatGrossDlyByte_MASK 0x3 |
| 381 | #define DWDTC_WrDatGrossDlyByte_NO_DELAY 0 |
| 382 | #define DWDTC_WrDatGrossDlyByte_0_5_ 1 |
| 383 | #define DWDTC_WrDatGrossDlyByte_1 2 |
| 384 | #define DWDTC_WrDatFineDlyByte1_SHIFT 8 |
| 385 | #define DWDTC_WrDatGrossDlyByte1_SHIFT 13 |
| 386 | #define DWDTC_WrDatFineDlyByte2_SHIFT 16 |
| 387 | #define DWDTC_WrDatGrossDlyByte2_SHIFT 21 |
| 388 | #define DWDTC_WrDatFineDlyByte3_SHIFT 24 |
| 389 | #define DWDTC_WrDatGrossDlyByte3_SHIFT 29 |
| 390 | |
| 391 | #define DRAM_WRITE_DATA_TIMING_CTRL_HIGH 0x02 |
| 392 | #define DWDTC_WrDatFineDlyByte4_SHIFT 0 |
| 393 | #define DWDTC_WrDatGrossDlyByte4_SHIFT 5 |
| 394 | #define DWDTC_WrDatFineDlyByte5_SHIFT 8 |
| 395 | #define DWDTC_WrDatGrossDlyByte5_SHIFT 13 |
| 396 | #define DWDTC_WrDatFineDlyByte6_SHIFT 16 |
| 397 | #define DWDTC_WrDatGrossDlyByte6_SHIFT 21 |
| 398 | #define DWDTC_WrDatFineDlyByte7_SHIFT 24 |
| 399 | #define DWDTC_WrDatGrossDlyByte7_SHIFT 29 |
| 400 | |
| 401 | #define DRAM_WRITE_ECC_TIMING_CTRL 0x03 |
| 402 | #define DWETC_WrChkFinDly_SHIFT 0 |
| 403 | #define DWETC_WrChkGrossDly_SHIFT 5 |
| 404 | |
| 405 | #define DRAM_ADDR_CMD_TIMING_CTRL 0x04 |
| 406 | #define DACTC_CkeFineDelay_SHIFT 0 |
| 407 | #define DACTC_CkeFineDelay_MASK 0x1f |
| 408 | #define DACTC_CkeFineDelay_BASE 0 |
| 409 | #define DACTC_CkeFineDelay_MIN 0 |
| 410 | #define DACTC_CkeFineDelay_MAX 31 |
| 411 | #define DACTC_CkeSetup (1<<5) |
| 412 | #define DACTC_CsOdtFineDelay_SHIFT 8 |
| 413 | #define DACTC_CsOdtFineDelay_MASK 0x1f |
| 414 | #define DACTC_CsOdtFineDelay_BASE 0 |
| 415 | #define DACTC_CsOdtFineDelay_MIN 0 |
| 416 | #define DACTC_CsOdtFineDelay_MAX 31 |
| 417 | #define DACTC_CsOdtSetup (1<<13) |
| 418 | #define DACTC_AddrCmdFineDelay_SHIFT 16 |
| 419 | #define DACTC_AddrCmdFineDelay_MASK 0x1f |
| 420 | #define DACTC_AddrCmdFineDelay_BASE 0 |
| 421 | #define DACTC_AddrCmdFineDelay_MIN 0 |
| 422 | #define DACTC_AddrCmdFineDelay_MAX 31 |
| 423 | #define DACTC_AddrCmdSetup (1<<21) |
| 424 | |
| 425 | #define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05 |
| 426 | #define DRDTC_RdDqsTimeByte0_SHIFT 0 |
| 427 | #define DRDTC_RdDqsTimeByte_MASK 0x3f |
| 428 | #define DRDTC_RdDqsTimeByte_BASE 0 |
| 429 | #define DRDTC_RdDqsTimeByte_MIN 0 |
| 430 | #define DRDTC_RdDqsTimeByte_MAX 63 // 1/128 MEMCLK |
| 431 | #define DRDTC_RdDqsTimeByte1_SHIFT 8 |
| 432 | #define DRDTC_RdDqsTimeByte2_SHIFT 16 |
| 433 | #define DRDTC_RdDqsTimeByte3_SHIFT 24 |
| 434 | |
| 435 | #define DRAM_READ_DQS_TIMING_CTRL_HIGH 0x06 |
| 436 | #define DRDTC_RdDqsTimeByte4_SHIFT 0 |
| 437 | #define DRDTC_RdDqsTimeByte5_SHIFT 8 |
| 438 | #define DRDTC_RdDqsTimeByte6_SHIFT 16 |
| 439 | #define DRDTC_RdDqsTimeByte7_SHIFT 24 |
| 440 | |
| 441 | #define DRAM_READ_DQS_ECC_TIMING_CTRL 0x07 |
| 442 | #define DRDETC_RdDqsTimeCheck_SHIFT 0 |
| 443 | |
| 444 | #define DRAM_PHY_CTRL 0x08 |
| 445 | #define DPC_WrtLvTrEn (1<<0) |
| 446 | #define DPC_WrtLvTrMode (1<<1) |
| 447 | #define DPC_TrNibbleSel (1<<2) |
| 448 | #define DPC_TrDimmSel_SHIFT 4 |
| 449 | #define DPC_TrDimmSel_MASK 3 /* 0-->dimm0, 1-->dimm1, 2--->dimm2, 3--->dimm3 */ |
| 450 | #define DPC_WrLvOdt_SHIFT 8 |
| 451 | #define DPC_WrLvOdt_MASK 0xf /* bit 0-->odt 0, ...*/ |
| 452 | #define DPC_WrLvODtEn (1<<12) |
| 453 | #define DPC_DqsRcvTrEn (1<<13) |
| 454 | #define DPC_DisAutoComp (1<<30) |
| 455 | #define DPC_AsyncCompUpdate (1<<31) |
| 456 | |
| 457 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_0 0x10 //DIMM0 Channel A |
| 458 | #define DDRETC_DqsRcvEnFineDelayByte0_SHIFT 0 |
| 459 | #define DDRETC_DqsRcvEnFineDelayByte0_MASK 0x1f |
| 460 | #define DDRETC_DqsRcvEnGrossDelayByte0_SHIFT 5 |
| 461 | #define DDRETC_DqsRcvEnGrossDelayByte0_MASK 0x3 |
| 462 | #define DDRETC_DqsRcvEnFineDelayByte1_SHIFT 8 |
| 463 | #define DDRETC_DqsRcvEnGrossDelayByte1_SHIFT 13 |
| 464 | #define DDRETC_DqsRcvEnFineDelayByte2_SHIFT 16 |
| 465 | #define DDRETC_DqsRcvEnGrossDelayByte2_SHIFT 21 |
| 466 | #define DDRETC_DqsRcvEnFineDelayByte3_SHIFT 24 |
| 467 | #define DDRETC_DqsRcvEnGrossDelayByte3_SHIFT 29 |
| 468 | |
| 469 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_1 0x11 //DIMM0 Channel A |
| 470 | #define DDRETC_DqsRcvEnFineDelayByte4_SHIFT 0 |
| 471 | #define DDRETC_DqsRcvEnGrossDelayByte4_SHIFT 5 |
| 472 | #define DDRETC_DqsRcvEnFineDelayByte5_SHIFT 8 |
| 473 | #define DDRETC_DqsRcvEnGrossDelayByte5_SHIFT 13 |
| 474 | #define DDRETC_DqsRcvEnFineDelayByte6_SHIFT 16 |
| 475 | #define DDRETC_DqsRcvEnGrossDelayByte6_SHIFT 21 |
| 476 | #define DDRETC_DqsRcvEnFineDelayByte7_SHIFT 24 |
| 477 | #define DDRETC_DqsRcvEnGrossDelayByte7_SHIFT 29 |
| 478 | |
| 479 | #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_0_0 0x12 |
| 480 | #define DDRETCE_WrChkFineDlyByte0_SHIFT 0 |
| 481 | #define DDRETCE_WrChkGrossDlyByte0_SHIFT 5 |
| 482 | |
| 483 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_2 0x20 //DIMM0 channel B |
| 484 | #define DDRETC_DqsRcvEnFineDelayByte8_SHIFT 0 |
| 485 | #define DDRETC_DqsRcvEnGrossDelayByte8_SHIFT 5 |
| 486 | #define DDRETC_DqsRcvEnFineDelayByte9_SHIFT 8 |
| 487 | #define DDRETC_DqsRcvEnGrossDelayByte9_SHIFT 13 |
| 488 | #define DDRETC_DqsRcvEnFineDelayByte10_SHIFT 16 |
| 489 | #define DDRETC_DqsRcvEnGrossDelayByte10_SHIFT 21 |
| 490 | #define DDRETC_DqsRcvEnFineDelayByte11_SHIFT 24 |
| 491 | #define DDRETC_DqsRcvEnGrossDelayByte11_SHIFT 29 |
| 492 | |
| 493 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_3 0x21 // DIMM0 Channel B |
| 494 | #define DDRETC_DqsRcvEnFineDelayByte12_SHIFT 0 |
| 495 | #define DDRETC_DqsRcvEnGrossDelayByte12_SHIFT 5 |
| 496 | #define DDRETC_DqsRcvEnFineDelayByte13_SHIFT 8 |
| 497 | #define DDRETC_DqsRcvEnGrossDelayByte13_SHIFT 13 |
| 498 | #define DDRETC_DqsRcvEnFineDelayByte14_SHIFT 16 |
| 499 | #define DDRETC_DqsRcvEnGrossDelayByte14_SHIFT 21 |
| 500 | #define DDRETC_DqsRcvEnFineDelayByte15_SHIFT 24 |
| 501 | #define DDRETC_DqsRcvEnGrossDelayByte15_SHIFT 29 |
| 502 | |
| 503 | #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_0_1 0x22 |
| 504 | #define DDRETCE_WrChkFineDlyByte1_SHIFT 0 |
| 505 | #define DDRETCE_WrChkGrossDlyByte1_SHIFT 5 |
| 506 | |
| 507 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_0 0x13 //DIMM1 |
| 508 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_1 0x14 |
| 509 | #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_1_0 0x15 |
| 510 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_2 0x23 |
| 511 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_3 0x24 |
| 512 | #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_1_1 0x25 |
| 513 | |
| 514 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_0 0x16 // DIMM2 |
| 515 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_1 0x17 |
| 516 | #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_2_0 0x18 |
| 517 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_2 0x26 |
| 518 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_3 0x27 |
| 519 | #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_2_1 0x28 |
| 520 | |
| 521 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_0 0x19 // DIMM3 |
| 522 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_1 0x1a |
| 523 | #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_3_0 0x1b |
| 524 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_2 0x29 |
| 525 | #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_3 0x2a |
| 526 | #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_3_1 0x2b |
| 527 | |
| 528 | /* 04.06.2006 19:12 */ |
| 529 | |
| 530 | #if 0 |
| 531 | //DDR3 |
| 532 | #define DRAM_DQS_WRITE_TIME_CTRL_0_0 0x30 //DIMM0 Channel A |
| 533 | #define DDWTC_WrDqsFineDlyByte0_SHIFT 0 |
| 534 | #define DDWTC_WrDqsFineDlyByte0_MASK 0x1f |
| 535 | #define DDWTC_WrDqsGrossDlyByte0_SHIFT 5 |
| 536 | #define DDWTC_WrDqsGrossDlyByte0_MASK 0x3 |
| 537 | #define DDWTC_WrDqsFineDlyByte1_SHIFT 8 |
| 538 | #define DDWTC_WrDqsGrossDlyByte1_SHIFT 13 |
| 539 | #define DDWTC_WrDqsFineDlyByte2_SHIFT 16 |
| 540 | #define DDWTC_WrDqsGrossDlyByte2_SHIFT 21 |
| 541 | #define DDWTC_WrDqsFineDlyByte3_SHIFT 24 |
| 542 | #define DDWTC_WrDqsGrossDlyByte3_SHIFT 29 |
| 543 | |
| 544 | #define DRAM_DQS_WRTIE_TIME_CTRL_0_1 0x31 //DIMM0 Channel A |
| 545 | #define DDWTC_WrDqsFineDlyByte4_SHIFT 0 |
| 546 | #define DDWTC_WrDqsGrossDlyByte4_SHIFT 5 |
| 547 | #define DDWTC_WrDqsFineDlyByte5_SHIFT 8 |
| 548 | #define DDWTC_WrDqsGrossDlyByte5_SHIFT 13 |
| 549 | #define DDWTC_WrDqsFineDlyByte6_SHIFT 16 |
| 550 | #define DDWTC_WrDqsGrossDlyByte6_SHIFT 21 |
| 551 | #define DDWTC_WrDqsFineDlyByte7_SHIFT 24 |
| 552 | #define DDWTC_WrDqsGrossDlyByte7_SHIFT 29 |
| 553 | |
| 554 | #define DRAM_DQS_WRITE_TIMING_CTRL_ECC_0_0 0x32 |
| 555 | #define DDWTCE_WrDqsChkFineDlyByte0_SHIFT 0 |
| 556 | #define DDWTCE_WrDqsChkGrossDlyByte0_SHIFT 5 |
| 557 | |
| 558 | #define DRAM_DQS_WRITE_TIME_CTRL_0_2 0x40 //DIMM0 Channel B |
| 559 | #define DDWTC_WrDqsFineDlyByte8_SHIFT 0 |
| 560 | #define DDWTC_WrDqsGrossDlyByte8_SHIFT 5 |
| 561 | #define DDWTC_WrDqsFineDlyByte9_SHIFT 8 |
| 562 | #define DDWTC_WrDqsGrossDlyByte9_SHIFT 13 |
| 563 | #define DDWTC_WrDqsFineDlyByte10_SHIFT 16 |
| 564 | #define DDWTC_WrDqsGrossDlyByte10_SHIFT 21 |
| 565 | #define DDWTC_WrDqsFineDlyByte11_SHIFT 24 |
| 566 | #define DDWTC_WrDqsGrossDlyByte11_SHIFT 29 |
| 567 | |
| 568 | #define DRAM_DQS_WRTIE_TIME_CTRL_0_3 0x41 //DIMM0 Channel B |
| 569 | #define DDWTC_WrDqsFineDlyByte12_SHIFT 0 |
| 570 | #define DDWTC_WrDqsGrossDlyByte12_SHIFT 5 |
| 571 | #define DDWTC_WrDqsFineDlyByte13_SHIFT 8 |
| 572 | #define DDWTC_WrDqsGrossDlyByte13_SHIFT 13 |
| 573 | #define DDWTC_WrDqsFineDlyByte14_SHIFT 16 |
| 574 | #define DDWTC_WrDqsGrossDlyByte14_SHIFT 21 |
| 575 | #define DDWTC_WrDqsFineDlyByte15_SHIFT 24 |
| 576 | #define DDWTC_WrDqsGrossDlyByte15_SHIFT 29 |
| 577 | |
| 578 | #define DRAM_DQS_WRITE_TIMING_CTRL_ECC_0_1 0x42 |
| 579 | #define DDWTCE_WrDqsChkFineDlyByte1_SHIFT 0 |
| 580 | #define DDWTCE_WrDqsChkGrossDlyByte1_SHIFT 5 |
| 581 | |
| 582 | #define DRAM_DQS_WRITE_TIME_CTRL_1_0 0x33 //DIMM1 Channel A |
| 583 | #define DRAM_DQS_WRTIE_TIME_CTRL_1_1 0x34 //DIMM1 Channel A |
| 584 | #define DRAM_DQS_WRITE_TIMING_CTRL_ECC_1_0 0x35 |
| 585 | #define DRAM_DQS_WRITE_TIME_CTRL_1_2 0x43 //DIMM1 Channel B |
| 586 | #define DRAM_DQS_WRTIE_TIME_CTRL_1_3 0x44 //DIMM1 Channel B |
| 587 | #define DRAM_DQS_WRITE_TIMING_CTRL_ECC_1_1 0x45 |
| 588 | #endif |
| 589 | |
| 590 | #define DRAM_PHASE_RECOVERY_CTRL_0 0x50 |
| 591 | #define DPRC_PhRecFineDlyByte0_SHIFT 0 |
| 592 | #define DDWTC_PhRecFineDlyByte0_MASK 0x1f |
| 593 | #define DDWTC_PhRecGrossDlyByte0_SHIFT 5 |
| 594 | #define DDWTC_PhRecGrossDlyByte0_MASK 0x3 |
| 595 | #define DDWTC_PhRecFineDlyByte1_SHIFT 8 |
| 596 | #define DDWTC_PhRecGrossDlyByte1_SHIFT 13 |
| 597 | #define DDWTC_PhRecFineDlyByte2_SHIFT 16 |
| 598 | #define DDWTC_PhRecGrossDlyByte2_SHIFT 21 |
| 599 | #define DDWTC_PhRecFineDlyByte3_SHIFT 24 |
| 600 | #define DDWTC_PhRecGrossDlyByte3_SHIFT 29 |
| 601 | |
| 602 | #define DRAM_PHASE_RECOVERY_CTRL_1 0x51 |
| 603 | #define DPRC_PhRecFineDlyByte4_SHIFT 0 |
| 604 | #define DDWTC_PhRecGrossDlyByte4_SHIFT 5 |
| 605 | #define DDWTC_PhRecFineDlyByte5_SHIFT 8 |
| 606 | #define DDWTC_PhRecGrossDlyByte5_SHIFT 13 |
| 607 | #define DDWTC_PhRecFineDlyByte6_SHIFT 16 |
| 608 | #define DDWTC_PhRecGrossDlyByte6_SHIFT 21 |
| 609 | #define DDWTC_PhRecFineDlyByte7_SHIFT 24 |
| 610 | #define DDWTC_PhRecGrossDlyByte7_SHIFT 29 |
| 611 | |
| 612 | #define DRAM_ECC_PHASE_RECOVERY_CTRL 0x52 |
| 613 | #define DEPRC_PhRecEccDlyByte0_SHIFT 0 |
| 614 | #define DEPRC_PhRecEccGrossDlyByte0_SHIFT 5 |
| 615 | |
| 616 | #define DRAM_WRITE_LEVEL_ERROR 0x53 /* read only */ |
| 617 | #define DWLE_WrLvErr_SHIFT 0 |
| 618 | #define DWLE_WrLvErr_MASK 0xff |
| 619 | |
| 620 | #define DRAM_CTRL_MISC 0xa0 |
| 621 | #define DCM_MemCleared (1<<0) /* RD == F2x110 [MemCleared] */ |
| 622 | #define DCM_DramEnabled (1<<9) /* RD == F2x110 [DramEnabled] */ |
| 623 | |
| 624 | #define NB_TIME_STAMP_COUNT_LOW 0xb0 |
| 625 | #define TscLow_SHIFT 0 |
| 626 | #define TscLow_MASK 0xffffffff |
| 627 | |
| 628 | #define NB_TIME_STAMP_COUNT_HIGH 0xb4 |
| 629 | #define TscHigh_SHIFT 0 |
| 630 | #define TscHigh_Mask 0xff |
| 631 | |
| 632 | #define DCT_DEBUG_CTRL 0xf0 /* 0xf0 for DCT0, 0x1f0 is for DCT1*/ |
| 633 | #define DDC_DllAdjust_SHIFT 0 |
| 634 | #define DDC_DllAdjust_MASK 0xff |
| 635 | #define DDC_DllSlower (1<<8) |
| 636 | #define DDC_DllFaster (1<<9) |
| 637 | #define DDC_WrtDqsAdjust_SHIFT 16 |
| 638 | #define DDC_WrtDqsAdjust_MASK 0x7 |
| 639 | #define DDC_WrtDqsAdjustEn (1<<19) |
| 640 | |
| 641 | #define DRAM_CTRL_SEL_LOW 0x110 |
| 642 | #define DCSL_DctSelHiRngEn (1<<0) |
| 643 | #define DCSL_DctSelHi (1<<1) |
| 644 | #define DCSL_DctSelIntLvEn (1<<2) |
| 645 | #define DCSL_MemClrInit (1<<3) /* WR only */ |
| 646 | #define DCSL_DctGangEn (1<<4) |
| 647 | #define DCSL_DctDataIntLv (1<<5) |
| 648 | #define DCSL_DctSelIntLvAddr_SHIFT |
| 649 | #define DCSL_DctSelIntLvAddr_MASK 3 |
| 650 | #define DCSL_DramEnable (1<<8) /* RD only */ |
| 651 | #define DCSL_MemClrBusy (1<<9) /* RD only */ |
| 652 | #define DCSL_MemCleared (1<<10) /* RD only */ |
| 653 | #define DCSL_DctSelBaseAddr_47_27_SHIFT 11 |
| 654 | #define DCSL_DctSelBaseAddr_47_27_MASK 0x1fffff |
| 655 | |
| 656 | #define DRAM_CTRL_SEL_HIGH 0x114 |
| 657 | #define DCSH_DctSelBaseOffset_47_26_SHIFT 10 |
| 658 | #define DCSH_DctSelBaseOffset_47_26_MASK 0x3fffff |
| 659 | |
| 660 | #define MEM_CTRL_CONF_LOW 0x118 |
| 661 | #define MCCL_MctPriCpuRd (1<<0) |
| 662 | #define MCCL_MctPriCpuWr (1<<1) |
| 663 | #define MCCL_MctPriIsocRd_SHIFT 4 |
| 664 | #define MCCL_MctPriIsoc_MASK 0x3 |
| 665 | #define MCCL_MctPriIsocWr_SHIFT 6 |
| 666 | #define MCCL_MctPriIsocWe_MASK 0x3 |
| 667 | #define MCCL_MctPriDefault_SHIFT 8 |
| 668 | #define MCCL_MctPriDefault_MASK 0x3 |
| 669 | #define MCCL_MctPriWr_SHIFT 10 |
| 670 | #define MCCL_MctPriWr_MASK 0x3 |
| 671 | #define MCCL_MctPriIsoc_SHIFT 12 |
| 672 | #define MCCL_MctPriIsoc_MASK 0x3 |
| 673 | #define MCCL_MctPriTrace_SHIFT 14 |
| 674 | #define MCCL_MctPriTrace_MASK 0x3 |
| 675 | #define MCCL_MctPriScrub_SHIFT 16 |
| 676 | #define MCCL_MctPriScrub_MASK 0x3 |
| 677 | #define MCCL_McqMedPriByPassMax_SHIFT 20 |
| 678 | #define MCCL_McqMedPriByPassMax_MASK 0x7 |
| 679 | #define MCCL_McqHiPriByPassMax_SHIFT 24 |
| 680 | #define MCCL_McqHiPriByPassMax_MASK 0x7 |
| 681 | #define MCCL_MctVarPriCntLmt_SHIFT 28 |
| 682 | #define MCCL_MctVarPriCntLmt_MASK 0x7 |
| 683 | |
| 684 | #define MEM_CTRL_CONF_HIGH 0x11c |
| 685 | #define MCCH_DctWrLimit_SHIFT 0 |
| 686 | #define MCCH_DctWrLimit_MASK 0x3 |
| 687 | #define MCCH_MctWrLimit_SHIFT 2 |
| 688 | #define MCCH_MctWrLimit_MASK 0x1f |
| 689 | #define MCCH_MctPrefReqLimit_SHIFT 7 |
| 690 | #define MCCH_MctPrefReqLimit_MASK 0x1f |
| 691 | #define MCCH_PrefCpuDis (1<<12) |
| 692 | #define MCCH_PrefIoDis (1<<13) |
| 693 | #define MCCH_PrefIoFixStrideEn (1<<14) |
| 694 | #define MCCH_PrefFixStrideEn (1<<15) |
| 695 | #define MCCH_PrefFixDist_SHIFT 16 |
| 696 | #define MCCH_PrefFixDist_MASK 0x3 |
| 697 | #define MCCH_PrefConfSat_SHIFT 18 |
| 698 | #define MCCH_PrefConfSat_MASK 0x3 |
| 699 | #define MCCH_PrefOneConf_SHIFT 20 |
| 700 | #define MCCH_PrefOneConf_MASK 0x3 |
| 701 | #define MCCH_PrefTwoConf_SHIFT 22 |
| 702 | #define MCCH_PrefTwoConf_MASK 0x7 |
| 703 | #define MCCH_PrefThreeConf_SHIFT 25 |
| 704 | #define MCCH_prefThreeConf_MASK 0x7 |
| 705 | #define MCCH_PrefDramTrainMode (1<<28) |
| 706 | #define MCCH_FlushWrOnStpGnt (1<<29) |
| 707 | #define MCCH_FlushWr (1<<30) |
| 708 | #define MCCH_MctScrubEn (1<<31) |
| 709 | |
| 710 | |
| 711 | /* Function 3 */ |
| 712 | #define MCA_NB_CONTROL 0x40 |
| 713 | #define MNCT_CorrEccEn (1<<0) |
| 714 | #define MNCT_UnCorrEccEn (1<<1) |
| 715 | #define MNCT_CrcErr0En (1<<2) /* Link 0 */ |
| 716 | #define MNCT_CrcErr1En (1<<3) |
| 717 | #define MNCT_CrcErr2En (1<<4) |
| 718 | #define MBCT_SyncPkt0En (1<<5) /* Link 0 */ |
| 719 | #define MBCT_SyncPkt1En (1<<6) |
| 720 | #define MBCT_SyncPkt2En (1<<7) |
| 721 | #define MBCT_MstrAbrtEn (1<<8) |
| 722 | #define MBCT_TgtAbrtEn (1<<9) |
| 723 | #define MBCT_GartTblEkEn (1<<10) |
| 724 | #define MBCT_AtomicRMWEn (1<<11) |
| 725 | #define MBCT_WdogTmrRptEn (1<<12) |
| 726 | #define MBCT_DevErrEn (1<<13) |
| 727 | #define MBCT_L3ArrayCorEn (1<<14) |
| 728 | #define MBCT_L3ArrayUncEn (1<<15) |
| 729 | #define MBCT_HtProtEn (1<<16) |
| 730 | #define MBCT_HtDataEn (1<<17) |
| 731 | #define MBCT_DramParEn (1<<18) |
| 732 | #define MBCT_RtryHt0En (1<<19) /* Link 0 */ |
| 733 | #define MBCT_RtryHt1En (1<<20) |
| 734 | #define MBCT_RtryHt2En (1<<21) |
| 735 | #define MBCT_RtryHt3En (1<<22) |
| 736 | #define MBCT_CrcErr3En (1<<23) /* Link 3*/ |
| 737 | #define MBCT_SyncPkt3En (1<<24) /* Link 4 */ |
| 738 | #define MBCT_McaUsPwDatErrEn (1<<25) |
| 739 | #define MBCT_NbArrayParEn (1<<26) |
| 740 | #define MBCT_TblWlkDatErrEn (1<<27) |
| 741 | #define MBCT_FbDimmCorErrEn (1<<28) |
| 742 | #define MBCT_FbDimmUnCorErrEn (1<<29) |
| 743 | |
| 744 | |
| 745 | |
| 746 | #define MCA_NB_CONFIG 0x44 |
| 747 | #define MNC_CpuRdDatErrEn (1<<1) |
| 748 | #define MNC_SyncOnUcEccEn (1<<2) |
| 749 | #define MNC_SynvPktGenDis (1<<3) |
| 750 | #define MNC_SyncPktPropDis (1<<4) |
| 751 | #define MNC_IoMstAbortDis (1<<5) |
| 752 | #define MNC_CpuErrDis (1<<6) |
| 753 | #define MNC_IoErrDis (1<<7) |
| 754 | #define MNC_WdogTmrDis (1<<8) |
| 755 | #define MNC_WdogTmrCntSel_2_0_SHIFT 9 /* 3 is ar f3x180 */ |
| 756 | #define MNC_WdogTmrCntSel_2_0_MASK 0x3 |
| 757 | #define MNC_WdogTmrBaseSel_SHIFT 12 |
| 758 | #define MNC_WdogTmrBaseSel_MASK 0x3 |
| 759 | #define MNC_LdtLinkSel_SHIFT 14 |
| 760 | #define MNC_LdtLinkSel_MASK 0x3 |
| 761 | #define MNC_GenCrcErrByte0 (1<<16) |
| 762 | #define MNC_GenCrcErrByte1 (1<<17) |
| 763 | #define MNC_SubLinkSel_SHIFT 18 |
| 764 | #define MNC_SubLinkSel_MASK 0x3 |
| 765 | #define MNC_SyncOnWdogEn (1<<20) |
| 766 | #define MNC_SyncOnAnyErrEn (1<<21) |
| 767 | #define MNC_DramEccEn (1<<22) |
| 768 | #define MNC_ChipKillEccEn (1<<23) |
| 769 | #define MNC_IoRdDatErrEn (1<<24) |
| 770 | #define MNC_DisPciCfgCpuErrRsp (1<<25) |
| 771 | #define MNC_CorrMcaExcEn (1<<26) |
| 772 | #define MNC_NbMcaToMstCpuEn (1<<27) |
| 773 | #define MNC_DisTgtAbtCpuErrRsp (1<<28) |
| 774 | #define MNC_DisMstAbtCpuErrRsp (1<<29) |
| 775 | #define MNC_SyncOnDramAdrParErrEn (1<<30) |
| 776 | #define MNC_NbMcaLogEn (1<<31) |
| 777 | |
| 778 | #define MCA_NB_STATUS_LOW 0x48 |
| 779 | #define MNSL_ErrorCode_SHIFT 0 |
| 780 | #define MNSL_ErrorCode_MASK 0xffff |
| 781 | #define MNSL_ErrorCodeExt_SHIFT 16 |
| 782 | #define MNSL_ErrorCodeExt_MASK 0x1f |
| 783 | #define MNSL_Syndrome_15_8_SHIFT 24 |
| 784 | #define MNSL_Syndrome_15_8_MASK 0xff |
| 785 | |
| 786 | #define MCA_NB_STATUS_HIGH 0x4c |
| 787 | #define MNSH_ErrCPU_SHIFT 0 |
| 788 | #define MNSH_ErrCPU_MASK 0xf |
| 789 | #define MNSH_LDTLink_SHIFT 4 |
| 790 | #define MNSH_LDTLink_MASK 0xf |
| 791 | #define MNSH_ErrScrub (1<<8) |
| 792 | #define MNSH_SubLink (1<<9) |
| 793 | #define MNSH_McaStatusSubCache_SHIFT 10 |
| 794 | #define MNSH_McaStatusSubCache_MASK 0x3 |
| 795 | #define MNSH_Deffered (1<<12) |
| 796 | #define MNSH_UnCorrECC (1<<13) |
| 797 | #define MNSH_CorrECC (1<<14) |
| 798 | #define MNSH_Syndrome_7_0_SHIFT 15 |
| 799 | #define MNSH_Syndrome_7_0_MASK 0xff |
| 800 | #define MNSH_PCC (1<<25) |
| 801 | #define MNSH_ErrAddrVal (1<<26) |
| 802 | #define MNSH_ErrMiscVal (1<<27) |
| 803 | #define MNSH_ErrEn (1<<28) |
| 804 | #define MNSH_ErrUnCorr (1<<29) |
| 805 | #define MNSH_ErrOver (1<<30) |
| 806 | #define MNSH_ErrValid (1<<31) |
| 807 | |
| 808 | #define MCA_NB_ADDR_LOW 0x50 |
| 809 | #define MNAL_ErrAddr_31_1_SHIFT 1 |
| 810 | #define MNAL_ErrAddr_31_1_MASK 0x7fffffff |
| 811 | |
| 812 | #define MCA_NB_ADDR_HIGH 0x54 |
| 813 | #define MNAL_ErrAddr_47_32_SHIFT 0 |
| 814 | #define MNAL_ErrAddr_47_32_MASK 0xffff |
| 815 | |
| 816 | #define DRAM_SCRUB_RATE_CTRL 0x58 |
| 817 | #define SCRUB_NONE 0 |
| 818 | #define SCRUB_40ns 1 |
| 819 | #define SCRUB_80ns 2 |
| 820 | #define SCRUB_160ns 3 |
| 821 | #define SCRUB_320ns 4 |
| 822 | #define SCRUB_640ns 5 |
| 823 | #define SCRUB_1_28us 6 |
| 824 | #define SCRUB_2_56us 7 |
| 825 | #define SCRUB_5_12us 8 |
| 826 | #define SCRUB_10_2us 9 |
| 827 | #define SCRUB_20_5us 0xa |
| 828 | #define SCRUB_41_0us 0xb |
| 829 | #define SCRUB_81_9us 0xc |
| 830 | #define SCRUB_163_8us 0xd |
| 831 | #define SCRUB_327_7us 0xe |
| 832 | #define SCRUB_655_4us 0xf |
| 833 | #define SCRUB_1_31ms 0x10 |
| 834 | #define SCRUB_2_62ms 0x11 |
| 835 | #define SCRUB_5_24ms 0x12 |
| 836 | #define SCRUB_10_49ms 0x13 |
| 837 | #define SCRUB_20_97ms 0x14 |
| 838 | #define SCRUB_42ms 0x15 |
| 839 | #define SCRUB_84ms 0x16 |
| 840 | #define DSRC_DramScrub_SHFIT 0 |
| 841 | #define DSRC_DramScrub_MASK 0x1f |
| 842 | #define DSRC_L2Scrub_SHIFT 8 |
| 843 | #define DSRC_L2Scrub_MASK 0x1f |
| 844 | #define DSRC_DcacheScrub_SHIFT 16 |
| 845 | #define DSRC_DcacheScrub_MASK 0x1f |
| 846 | #define DSRC_L3Scrub_SHIFT 24 |
| 847 | #define DSRC_L3Scrub_MASK 0x1f |
| 848 | |
| 849 | #define DRAM_SCRUB_ADDR_LOW 0x5C |
| 850 | #define DSAL_ScrubReDirEn (1<<0) |
| 851 | #define DSAL_ScrubAddrLo_SHIFT 6 |
| 852 | #define DSAL_ScrubAddrLo_MASK 0x3ffffff |
| 853 | |
| 854 | #define DRAM_SCRUB_ADDR_HIGH 0x60 |
| 855 | #define DSAH_ScrubAddrHi_SHIFT 0 |
| 856 | #define DSAH_ScrubAddrHi_MASK 0xffff |
| 857 | |
| 858 | #define HW_THERMAL_CTRL 0x64 |
| 859 | |
| 860 | #define SW_THERMAL_CTRL 0x68 |
| 861 | |
| 862 | #define DATA_BUF_CNT 0x6c |
| 863 | |
| 864 | #define SRI_XBAR_CMD_BUF_CNT 0x70 |
| 865 | |
| 866 | #define XBAR_SRI_CMD_BUF_CNT 0x74 |
| 867 | |
| 868 | #define MCT_XBAR_CMD_BUF_CNT 0x78 |
| 869 | |
| 870 | #define ACPI_PWR_STATE_CTRL 0x80 /* till 0x84 */ |
| 871 | |
| 872 | #define NB_CONFIG_LOW 0x88 |
| 873 | #define NB_CONFIG_HIGH 0x8c |
| 874 | |
| 875 | #define GART_APERTURE_CTRL 0x90 |
| 876 | |
| 877 | #define GART_APERTURE_BASE 0x94 |
| 878 | |
| 879 | #define GART_TBL_BASE 0x98 |
| 880 | |
| 881 | #define GART_CACHE_CTRL 0x9c |
| 882 | |
| 883 | #define PWR_CTRL_MISC 0xa0 |
| 884 | |
| 885 | #define RPT_TEMP_CTRL 0xa4 |
| 886 | |
| 887 | #define ON_LINE_SPARE_CTRL 0xb0 |
| 888 | |
| 889 | #define SBI_P_STATE_LIMIT 0xc4 |
| 890 | |
| 891 | #define CLK_PWR_TIMING_CTRL0 0xd4 |
| 892 | #define CLK_PWR_TIMING_CTRL1 0xd8 |
| 893 | #define CLK_PWR_TIMING_CTRL2 0xdc |
| 894 | |
| 895 | #define THERMTRIP_STATUS 0xE4 |
| 896 | |
| 897 | |
| 898 | #define NORTHBRIDGE_CAP 0xE8 |
| 899 | #define NBCAP_TwoChanDRAMcap (1 << 0) |
| 900 | #define NBCAP_DualNodeMPcap (1 << 1) |
| 901 | #define NBCAP_EightNodeMPcap (1 << 2) |
| 902 | #define NBCAP_ECCcap (1 << 3) |
| 903 | #define NBCAP_ChipkillECCcap (1 << 4) |
| 904 | #define NBCAP_DdrMaxRate_SHIFT 5 |
| 905 | #define NBCAP_DdrMaxRate_MASK 7 |
| 906 | #define NBCAP_DdrMaxRate_400 7 |
| 907 | #define NBCAP_DdrMaxRate_533 6 |
| 908 | #define NBCAP_DdrMaxRate_667 5 |
| 909 | #define NBCAP_DdrMaxRate_800 4 |
| 910 | #define NBCAP_DdrMaxRate_1067 3 |
| 911 | #define NBCAP_DdrMaxRate_1333 2 |
| 912 | #define NBCAP_DdrMaxRate_1600 1 |
| 913 | #define NBCAP_DdrMaxRate_3_2G 6 |
| 914 | #define NBCAP_DdrMaxRate_4_0G 5 |
| 915 | #define NBCAP_DdrMaxRate_4_8G 4 |
| 916 | #define NBCAP_DdrMaxRate_6_4G 3 |
| 917 | #define NBCAP_DdrMaxRate_8_0G 2 |
| 918 | #define NBCAP_DdrMaxRate_9_6G 1 |
| 919 | #define NBCAP_Mem_ctrl_cap (1 << 8) |
| 920 | #define MBCAP_SVMCap (1<<9) |
| 921 | #define NBCAP_HtcCap (1<<10) |
| 922 | #define NBCAP_CmpCap_SHIFT 12 |
| 923 | #define NBCAP_CmpCap_MASK 3 |
| 924 | #define NBCAP_MpCap_SHIFT 16 |
| 925 | #define NBCAP_MpCap_MASK 7 |
| 926 | #define NBCAP_MpCap_1N 7 |
| 927 | #define NBCAP_MpCap_2N 6 |
| 928 | #define NBCAP_MpCap_4N 5 |
| 929 | #define NBCAP_MpCap_8N 4 |
| 930 | #define NBCAP_MpCap_32N 0 |
| 931 | #define NBCAP_UnGangEn_SHIFT 20 |
| 932 | #define NBCAP_UnGangEn_MASK 0xf |
| 933 | #define NBCAP_L3Cap (1<<25) |
| 934 | #define NBCAP_HtAcCap (1<<26) |
| 935 | |
| 936 | /* 04/04/2006 18:00 */ |
| 937 | |
| 938 | #define EXT_NB_MCA_CTRL 0x180 |
| 939 | |
| 940 | #define NB_EXT_CONF 0x188 |
| 941 | #define DOWNCORE_CTRL 0x190 |
| 942 | #define DWNCC_DisCore_SHIFT 0 |
| 943 | #define DWNCC_DisCore_MASK 0xf |
| 944 | |
| 945 | /* Function 5 for FBDIMM */ |
| 946 | #define FBD_DRAM_TIMING_LOW |
| 947 | |
| 948 | #define LinkConnected (1 << 0) |
| 949 | #define InitComplete (1 << 1) |
| 950 | #define NonCoherent (1 << 2) |
| 951 | #define ConnectionPending (1 << 4) |
| 952 | |
| 953 | // Use the LAPIC timer count register to hold each core's init status |
| 954 | // Format: byte 0 - state |
| 955 | // byte 1 - fid_max |
| 956 | // byte 2 - nb_cof_vid_update |
| 957 | // byte 3 - apic id |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 958 | |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 959 | #define LAPIC_MSG_REG 0x380 |
| 960 | #define F10_APSTATE_STARTED 0x13 // start of AP execution |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 961 | #define F10_APSTATE_ASLEEP 0x14 // AP sleeping |
| 962 | #define F10_APSTATE_STOPPED 0x15 // allow AP to stop |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 963 | #define F10_APSTATE_RESET 0x01 // waiting for warm reset |
| 964 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 965 | #define MAX_CORES_SUPPORTED 128 |
| 966 | |
stepan | 8301d83 | 2010-12-08 07:07:33 +0000 | [diff] [blame] | 967 | #include "nums.h" |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 968 | |
| 969 | #ifdef __PRE_RAM__ |
| 970 | #if NODE_NUMS==64 |
| 971 | #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) |
| 972 | #else |
| 973 | #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) |
| 974 | #endif |
| 975 | #endif |
| 976 | |
| 977 | #include "raminit.h" |
| 978 | |
Timothy Pearson | 620fa5f | 2015-03-27 22:50:09 -0500 | [diff] [blame] | 979 | #include "../amdmct/wrappers/mcti.h" |
Kyösti Mälkki | 5ef269b | 2015-02-22 00:09:14 +0200 | [diff] [blame] | 980 | #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 981 | #include "../amdmct/mct_ddr3/mct_d.h" |
Kyösti Mälkki | 5ef269b | 2015-02-22 00:09:14 +0200 | [diff] [blame] | 982 | #else |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 983 | #include "../amdmct/mct/mct_d.h" |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 984 | #endif |
| 985 | |
| 986 | struct link_pair_t { |
| 987 | device_t udev; |
| 988 | u32 upos; |
| 989 | u32 uoffs; |
| 990 | device_t dev; |
| 991 | u32 pos; |
| 992 | u32 offs; |
| 993 | u8 host; |
| 994 | u8 nodeid; |
| 995 | u8 linkn; |
| 996 | u8 rsv; |
| 997 | } __attribute__((packed)); |
| 998 | |
| 999 | struct nodes_info_t { |
| 1000 | u32 nodes_in_group; // could be 2, 3, 4, 5, 6, 7, 8 |
| 1001 | u32 groups_in_plane; // could be 1, 2, 3, 4, 5 |
| 1002 | u32 planes; // could be 1, 2 |
| 1003 | u32 up_planes; // down planes will be [up_planes, planes) |
| 1004 | } __attribute__((packed)); |
| 1005 | |
Timothy Pearson | 586d6e2 | 2015-02-16 14:57:06 -0600 | [diff] [blame] | 1006 | struct ht_link_config { |
Timothy Pearson | 8ac4929 | 2015-09-07 15:55:50 -0500 | [diff] [blame] | 1007 | uint32_t ht_speed_limit; // Speed in MHz; 0 for autodetect (default) |
Timothy Pearson | 586d6e2 | 2015-02-16 14:57:06 -0600 | [diff] [blame] | 1008 | }; |
| 1009 | |
Furquan Shaikh | 20f25dd | 2014-04-22 10:41:05 -0700 | [diff] [blame] | 1010 | /* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/ |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 1011 | |
| 1012 | struct sys_info { |
| 1013 | int32_t needs_reset; |
| 1014 | |
| 1015 | u8 ln[NODE_NUMS*NODE_NUMS];// [0, 3] link n, [4, 7] will be hop num |
| 1016 | u16 ln_tn[NODE_NUMS*8]; // for 0x0zzz: bit [0,7] target node num, bit[8,11] respone link from target num; 0x80ff mean not inited, 0x4yyy mean non coherent and yyy is link pair index |
| 1017 | struct nodes_info_t nodes_info; |
| 1018 | u32 nodes; |
| 1019 | |
| 1020 | u8 host_link_freq[NODE_NUMS*8]; // record freq for every link from cpu, 0x0f means don't need to touch it |
| 1021 | u16 host_link_freq_cap[NODE_NUMS*8]; //cap |
| 1022 | |
Timothy Pearson | 586d6e2 | 2015-02-16 14:57:06 -0600 | [diff] [blame] | 1023 | struct ht_link_config ht_link_cfg; |
| 1024 | |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 1025 | u32 segbit; |
| 1026 | u32 sbdn; |
| 1027 | u32 sblk; |
| 1028 | u32 sbbusn; |
| 1029 | |
| 1030 | u32 ht_c_num; |
| 1031 | u32 ht_c_conf_bus[HC_NUMS]; // 4-->32 |
| 1032 | |
| 1033 | struct link_pair_t link_pair[HC_NUMS*4];// enough? only in_conherent, 32 chain and every chain have 4 HT device |
| 1034 | u32 link_pair_num; |
| 1035 | |
| 1036 | struct mem_controller ctrl[NODE_NUMS]; |
| 1037 | |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 1038 | struct MCTStatStruc MCTstat; |
| 1039 | struct DCTStatStruc DCTstatA[NODE_NUMS]; |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 1040 | } __attribute__((packed)); |
| 1041 | |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 1042 | #ifdef __PRE_RAM__ |
| 1043 | extern struct sys_info sysinfo_car; |
| 1044 | #endif |
| 1045 | |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 1046 | #ifndef __PRE_RAM__ |
| 1047 | device_t get_node_pci(u32 nodeid, u32 fn); |
| 1048 | #endif |
| 1049 | |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 1050 | #ifdef __PRE_RAM__ |
| 1051 | void showallroutes(int level, device_t dev); |
| 1052 | |
| 1053 | void setup_resource_map_offset(const u32 *register_values, u32 max, u32 |
| 1054 | offset_pci_dev, u32 offset_io_base); |
| 1055 | |
| 1056 | void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 |
| 1057 | offset_pci_dev, u32 offset_io_base); |
| 1058 | |
| 1059 | void setup_resource_map_x(const u32 *register_values, u32 max); |
| 1060 | |
| 1061 | /* reset_test.c */ |
| 1062 | u32 cpu_init_detected(u8 nodeid); |
| 1063 | u32 bios_reset_detected(void); |
| 1064 | u32 cold_reset_detected(void); |
| 1065 | u32 other_reset_detected(void); |
| 1066 | u32 get_sblk(void); |
| 1067 | u8 get_sbbusn(u8 sblk); |
| 1068 | #endif |
| 1069 | |
Scott Duplichan | 314dd0b | 2011-03-08 23:01:46 +0000 | [diff] [blame] | 1070 | #include "northbridge/amd/amdht/porting.h" |
| 1071 | BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List); |
| 1072 | |
Vladimir Serbinenko | 2a19fb1 | 2014-10-02 20:09:19 +0200 | [diff] [blame] | 1073 | struct acpi_rsdp; |
| 1074 | |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 1075 | unsigned long northbridge_write_acpi_tables(device_t device, |
| 1076 | unsigned long start, |
Vladimir Serbinenko | 2a19fb1 | 2014-10-02 20:09:19 +0200 | [diff] [blame] | 1077 | struct acpi_rsdp *rsdp); |
Alexander Couzens | 5eea458 | 2015-04-12 22:18:55 +0200 | [diff] [blame] | 1078 | void northbridge_acpi_write_vars(device_t device); |
Vladimir Serbinenko | 2a19fb1 | 2014-10-02 20:09:19 +0200 | [diff] [blame] | 1079 | |
Scott Duplichan | 1ba2eee | 2010-10-19 04:58:49 +0000 | [diff] [blame] | 1080 | #endif /* AMDFAM10_H */ |