Kyösti Mälkki | 1aa35c6 | 2014-10-21 14:19:04 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
Kyösti Mälkki | 1aa35c6 | 2014-10-21 14:19:04 +0300 | [diff] [blame] | 12 | */ |
Kyösti Mälkki | e68f4ff | 2014-10-22 15:53:34 +0300 | [diff] [blame] | 13 | |
| 14 | #include <console/console.h> |
Kyösti Mälkki | 1aa35c6 | 2014-10-21 14:19:04 +0300 | [diff] [blame] | 15 | #include <stdint.h> |
| 16 | #include <string.h> |
Kyösti Mälkki | e68f4ff | 2014-10-22 15:53:34 +0300 | [diff] [blame] | 17 | |
| 18 | #include <northbridge/amd/agesa/agesawrapper.h> |
| 19 | #include <northbridge/amd/agesa/BiosCallOuts.h> |
| 20 | #include "amdlib.h" |
Kyösti Mälkki | 1aa35c6 | 2014-10-21 14:19:04 +0300 | [diff] [blame] | 21 | #include "AGESA.h" |
| 22 | #include "AMD.h" |
| 23 | |
| 24 | |
| 25 | /* |
| 26 | * Possible AGESA_STATUS values: |
| 27 | * |
| 28 | * 0x0 = AGESA_SUCCESS |
| 29 | * 0x1 = AGESA_UNSUPPORTED |
| 30 | * 0x2 = AGESA_BOUNDS_CHK |
| 31 | * 0x3 = AGESA_ALERT |
| 32 | * 0x4 = AGESA_WARNING |
| 33 | * 0x5 = AGESA_ERROR |
| 34 | * 0x6 = AGESA_CRITICAL |
| 35 | * 0x7 = AGESA_FATAL |
| 36 | */ |
| 37 | static const char * decodeAGESA_STATUS(AGESA_STATUS sret) |
| 38 | { |
| 39 | const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED", |
| 40 | "AGESA_BOUNDS_CHK", "AGESA_ALERT", |
| 41 | "AGESA_WARNING", "AGESA_ERROR", |
| 42 | "AGESA_CRITICAL", "AGESA_FATAL" |
| 43 | }; |
| 44 | if (sret > 7) return "unknown"; /* Non-AGESA error code */ |
| 45 | return statusStrings[sret]; |
| 46 | } |
Kyösti Mälkki | e68f4ff | 2014-10-22 15:53:34 +0300 | [diff] [blame] | 47 | |
| 48 | #if 0 |
| 49 | |
| 50 | /** |
| 51 | * |
| 52 | */ |
| 53 | static void agesa_bound_check(EVENT_PARAMS *event) |
| 54 | { |
| 55 | switch (event->EventInfo) { |
| 56 | case CPU_ERROR_HEAP_IS_FULL: |
| 57 | printk(BIOS_DEBUG, "Heap allocation for specified buffer handle failed as heap is full\n"); |
| 58 | break; |
| 59 | |
| 60 | case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED: |
| 61 | printk(BIOS_DEBUG, "Allocation incomplete as buffer has previously been allocated\n"); |
| 62 | break; |
| 63 | |
| 64 | case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT: |
| 65 | printk(BIOS_DEBUG, "Unable to locate buffer handle or deallocate heap as buffer handle cannot be located\n"); |
| 66 | break; |
| 67 | |
| 68 | case CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT: |
| 69 | printk(BIOS_DEBUG, "Unable to locate pointer to the heap buffer\n"); |
| 70 | break; |
| 71 | |
| 72 | default: |
| 73 | break; |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | /** |
| 78 | * |
| 79 | */ |
| 80 | static void agesa_alert(EVENT_PARAMS *event) |
| 81 | { |
| 82 | switch (event->EventInfo) { |
| 83 | case MEM_ALERT_USER_TMG_MODE_OVERRULED: |
| 84 | printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " |
Kyösti Mälkki | 1aa35c6 | 2014-10-21 14:19:04 +0300 | [diff] [blame] | 85 | |
Kyösti Mälkki | e68f4ff | 2014-10-22 15:53:34 +0300 | [diff] [blame] | 86 | "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n", |
| 87 | (unsigned int)event->DataParam1, |
| 88 | (unsigned int)event->DataParam2, |
| 89 | (unsigned int)event->DataParam3); |
| 90 | break; |
| 91 | |
| 92 | case MEM_ALERT_ORG_MISMATCH_DIMM: |
| 93 | printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " |
| 94 | "DIMM organization miss-match\n", |
| 95 | (unsigned int)event->DataParam1, |
| 96 | (unsigned int)event->DataParam2, |
| 97 | (unsigned int)event->DataParam3); |
| 98 | break; |
| 99 | |
| 100 | case MEM_ALERT_BK_INT_DIS: |
| 101 | printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " |
| 102 | "Bank interleaving disable for internal issue\n", |
| 103 | (unsigned int)event->DataParam1, |
| 104 | (unsigned int)event->DataParam2, |
| 105 | (unsigned int)event->DataParam3); |
| 106 | break; |
| 107 | |
| 108 | case CPU_EVENT_BIST_ERROR: |
| 109 | printk(BIOS_DEBUG, "BIST error: %x reported on Socket %x Core %x\n", |
| 110 | (unsigned int)event->DataParam1, |
| 111 | (unsigned int)event->DataParam2, |
| 112 | (unsigned int)event->DataParam3); |
| 113 | break; |
| 114 | |
| 115 | case HT_EVENT_HW_SYNCFLOOD: |
| 116 | printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %x Link %x\n", |
| 117 | (unsigned int)event->DataParam1, |
| 118 | (unsigned int)event->DataParam2); |
| 119 | break; |
| 120 | |
| 121 | case HT_EVENT_HW_HTCRC: |
| 122 | printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %x Link %x Lanemask:%x\n", |
| 123 | (unsigned int)event->DataParam1, |
| 124 | (unsigned int)event->DataParam2, |
| 125 | (unsigned int)event->DataParam3); |
| 126 | break; |
| 127 | |
| 128 | default: |
| 129 | break; |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | /** |
| 134 | * |
| 135 | */ |
| 136 | static void agesa_warning(EVENT_PARAMS *event) |
| 137 | { |
| 138 | /* |
| 139 | if (event->EventInfo == CPU_EVENT_STACK_REENTRY) { |
| 140 | printk(BIOS_DEBUG, |
| 141 | "The stack has already been enabled and this is a |
| 142 | redundant invocation of AMD_ENABLE_STACK. There is no event logged and |
| 143 | no data values. The event sub-class is returned along with the status code\n"); |
| 144 | return; |
| 145 | } |
| 146 | */ |
| 147 | |
| 148 | switch (event->EventInfo >> 24) { |
| 149 | case 0x04: |
| 150 | printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", |
| 151 | (unsigned int)event->DataParam1, |
| 152 | (unsigned int)event->DataParam2, |
| 153 | (unsigned int)event->DataParam3); |
| 154 | break; |
| 155 | |
| 156 | case 0x08: |
| 157 | printk(BIOS_DEBUG, "Processor: "); |
| 158 | break; |
| 159 | |
| 160 | case 0x10: |
| 161 | printk(BIOS_DEBUG, "Hyper Transport: "); |
| 162 | break; |
| 163 | |
| 164 | default: |
| 165 | break; |
| 166 | } |
| 167 | |
| 168 | switch (event->EventInfo) { |
| 169 | case MEM_WARNING_UNSUPPORTED_QRDIMM: |
| 170 | printk(BIOS_DEBUG, "QR DIMMs detected but not supported\n"); |
| 171 | break; |
| 172 | |
| 173 | case MEM_WARNING_UNSUPPORTED_UDIMM: |
| 174 | printk(BIOS_DEBUG, "Unbuffered DIMMs detected but not supported\n"); |
| 175 | break; |
| 176 | |
| 177 | case MEM_WARNING_UNSUPPORTED_SODIMM: |
| 178 | printk(BIOS_DEBUG, "SO-DIMMs detected but not supported"); |
| 179 | break; |
| 180 | |
| 181 | case MEM_WARNING_UNSUPPORTED_X4DIMM: |
| 182 | printk(BIOS_DEBUG, "x4 DIMMs detected but not supported"); |
| 183 | break; |
| 184 | |
| 185 | case MEM_WARNING_UNSUPPORTED_RDIMM: |
| 186 | printk(BIOS_DEBUG, "Registered DIMMs detected but not supported"); |
| 187 | break; |
| 188 | |
| 189 | /* |
| 190 | case MEM_WARNING_UNSUPPORTED_LRDIMM: |
| 191 | printk(BIOS_DEBUG, "Load Reduced DIMMs detected but not supported"); |
| 192 | break; |
| 193 | */ |
| 194 | |
| 195 | case MEM_WARNING_NO_SPDTRC_FOUND: |
| 196 | printk(BIOS_DEBUG, "NO_SPDTRC_FOUND"); |
| 197 | break; |
| 198 | |
| 199 | case MEM_WARNING_EMP_NOT_SUPPORTED: |
| 200 | printk(BIOS_DEBUG, "Processor is not capable for EMP");// |
| 201 | break; |
| 202 | |
| 203 | case MEM_WARNING_EMP_CONFLICT: |
| 204 | printk(BIOS_DEBUG, "EMP cannot be enabled if channel interleaving bank interleaving, or bank swizzle is enabled\n");// |
| 205 | break; |
| 206 | |
| 207 | case MEM_WARNING_EMP_NOT_ENABLED: |
| 208 | printk(BIOS_DEBUG, "Memory size is not power of two\n");// |
| 209 | break; |
| 210 | |
| 211 | case MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED: |
| 212 | printk(BIOS_DEBUG, "MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED\n"); |
| 213 | break; |
| 214 | |
| 215 | case MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED: |
| 216 | printk(BIOS_DEBUG, "MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED\n"); |
| 217 | break; |
| 218 | |
| 219 | case MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED: |
| 220 | printk(BIOS_DEBUG, "MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED\n"); |
| 221 | break; |
| 222 | |
| 223 | case MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED: |
| 224 | printk(BIOS_DEBUG, "MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED\n"); |
| 225 | break; |
| 226 | |
| 227 | case MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED: |
| 228 | printk(BIOS_DEBUG, "MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED\n"); |
| 229 | break; |
| 230 | |
| 231 | /* |
| 232 | case MEM_WARNING_INITIAL_DDR3VOLT_NONZERO: |
| 233 | printk(BIOS_DEBUG, "MEM_WARNING_INITIAL_DDR3VOLT_NONZERO\n"); |
| 234 | break; |
| 235 | |
| 236 | case MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO: |
| 237 | printk(BIOS_DEBUG, "MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO\n"); |
| 238 | break; |
| 239 | */ |
| 240 | |
| 241 | case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: |
| 242 | printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); |
| 243 | if ((event->EventInfo & 0x000000FF) == 0x01) { |
| 244 | printk(BIOS_DEBUG, "AGESA_CACHE_SIZE_REDUCED\n"); |
| 245 | } else if ((event->EventInfo & 0x000000FF) == 0x02) { |
| 246 | printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_1MB\n"); |
| 247 | } else if ((event->EventInfo & 0x000000FF) == 0x03) { |
| 248 | printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_4GB\n"); |
| 249 | } |
| 250 | printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", |
| 251 | (unsigned int)event->DataParam1, |
| 252 | (unsigned int)event->DataParam2, |
| 253 | (unsigned int)event->DataParam3); |
| 254 | break; |
| 255 | |
| 256 | case CPU_WARNING_ADJUSTED_LEVELING_MODE: |
| 257 | printk(BIOS_DEBUG, "CPU_WARNING_ADJUSTED_LEVELING_MODE " |
| 258 | "requested: %x, actual level:%x\n", |
| 259 | (unsigned int)event->DataParam1, |
| 260 | (unsigned int)event->DataParam2); |
| 261 | break; |
| 262 | |
| 263 | case CPU_EVENT_PM_PSTATE_OVERCURRENT: |
| 264 | printk(BIOS_DEBUG, "CPU_EVENT_PM_PSTATE_OVERCURRENT " |
| 265 | "Socket: %x, Pstate:%x\n", |
| 266 | (unsigned int)event->DataParam1, |
| 267 | (unsigned int)event->DataParam2); |
| 268 | break; |
| 269 | |
| 270 | case CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG: |
| 271 | printk(BIOS_DEBUG, "CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG\n"); |
| 272 | break; |
| 273 | |
| 274 | /* |
| 275 | case CPU_EVENT_UNKNOWN_PROCESSOR_REVISION: |
| 276 | printk(BIOS_DEBUG, "CPU_EVENT_UNKNOWN_PROCESSOR_REVISION, socket: %lx, cpuid:%lx\n", |
| 277 | event->DataParam1, |
| 278 | event->DataParam2); |
| 279 | break; |
| 280 | */ |
| 281 | |
| 282 | case HT_EVENT_OPT_REQUIRED_CAP_RETRY: |
| 283 | printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %lx Link %lx Depth %lx\n", |
| 284 | event->DataParam1, |
| 285 | event->DataParam2, |
| 286 | event->DataParam3); |
| 287 | break; |
| 288 | |
| 289 | case HT_EVENT_OPT_REQUIRED_CAP_GEN3: |
| 290 | printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %x Link %x Depth %x\n", |
| 291 | (unsigned int)event->DataParam1, |
| 292 | (unsigned int)event->DataParam2, |
| 293 | (unsigned int)event->DataParam3); |
| 294 | break; |
| 295 | |
| 296 | case HT_EVENT_OPT_UNUSED_LINKS: |
| 297 | printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%x LinkA%x SocketB%x LinkB%x\n", |
| 298 | (unsigned int)event->DataParam1, |
| 299 | (unsigned int)event->DataParam2, |
| 300 | (unsigned int)event->DataParam3, |
| 301 | (unsigned int)event->DataParam4); |
| 302 | break; |
| 303 | |
| 304 | case HT_EVENT_OPT_LINK_PAIR_EXCEED: |
| 305 | printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%x MasterLink%x SocketB%x AltLink%x\n", |
| 306 | |
| 307 | (unsigned int)event->DataParam1, |
| 308 | (unsigned int)event->DataParam2, |
| 309 | (unsigned int)event->DataParam3, |
| 310 | (unsigned int)event->DataParam4); |
| 311 | default: |
| 312 | break; |
| 313 | } |
| 314 | } |
| 315 | |
| 316 | /** |
| 317 | * |
| 318 | */ |
| 319 | static void agesa_error(EVENT_PARAMS *event) |
| 320 | { |
| 321 | |
| 322 | switch (event->EventInfo >> 24) { |
| 323 | case 0x04: |
| 324 | printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", |
| 325 | (unsigned int)event->DataParam1, |
| 326 | (unsigned int)event->DataParam2, |
| 327 | (unsigned int)event->DataParam3); |
| 328 | break; |
| 329 | |
| 330 | case 0x08: |
| 331 | printk(BIOS_DEBUG, "Processor: "); |
| 332 | break; |
| 333 | |
| 334 | case 0x10: |
| 335 | printk(BIOS_DEBUG, "Hyper Transport: "); |
| 336 | break; |
| 337 | |
| 338 | default: |
| 339 | break; |
| 340 | } |
| 341 | |
| 342 | switch (event->EventInfo) { |
| 343 | case MEM_ERROR_NO_DQS_POS_RD_WINDOW: |
| 344 | printk(BIOS_DEBUG, "No DQS Position window for RD DQS\n"); |
| 345 | break; |
| 346 | |
| 347 | case MEM_ERROR_SMALL_DQS_POS_RD_WINDOW: |
| 348 | printk(BIOS_DEBUG, "Small DQS Position window for RD DQS\n"); |
| 349 | break; |
| 350 | |
| 351 | case MEM_ERROR_NO_DQS_POS_WR_WINDOW: |
| 352 | printk(BIOS_DEBUG, "No DQS Position window for WR DQS\n"); |
| 353 | break; |
| 354 | |
| 355 | case MEM_ERROR_SMALL_DQS_POS_WR_WINDOW: |
| 356 | printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n"); |
| 357 | break; |
| 358 | |
| 359 | case MEM_ERROR_DIMM_SPARING_NOT_ENABLED: |
| 360 | printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n"); |
| 361 | break; |
| 362 | |
| 363 | case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE: |
| 364 | printk(BIOS_DEBUG, "Receive Enable value is too large\n"); |
| 365 | break; |
| 366 | case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW: |
| 367 | printk(BIOS_DEBUG, "There is no DQS receiver enable window\n"); |
| 368 | break; |
| 369 | |
| 370 | case MEM_ERROR_DRAM_ENABLED_TIME_OUT: |
| 371 | printk(BIOS_DEBUG, "Time out when polling DramEnabled bit\n"); |
| 372 | break; |
| 373 | |
| 374 | case MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT: |
| 375 | printk(BIOS_DEBUG, "Time out when polling DctAccessDone bit\n"); |
| 376 | break; |
| 377 | |
| 378 | case MEM_ERROR_SEND_CTRL_WORD_TIME_OUT: |
| 379 | printk(BIOS_DEBUG, "Time out when polling SendCtrlWord bit\n"); |
| 380 | break; |
| 381 | |
| 382 | case MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT: |
| 383 | printk(BIOS_DEBUG, "Time out when polling PrefDramTrainMode bit\n"); |
| 384 | break; |
| 385 | |
| 386 | case MEM_ERROR_ENTER_SELF_REF_TIME_OUT: |
| 387 | printk(BIOS_DEBUG, "Time out when polling EnterSelfRef bit\n"); |
| 388 | break; |
| 389 | |
| 390 | case MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT: |
| 391 | printk(BIOS_DEBUG, "Time out when polling FreqChgInProg bit\n"); |
| 392 | break; |
| 393 | |
| 394 | case MEM_ERROR_EXIT_SELF_REF_TIME_OUT: |
| 395 | printk(BIOS_DEBUG, "Time out when polling ExitSelfRef bit\n"); |
| 396 | break; |
| 397 | |
| 398 | case MEM_ERROR_SEND_MRS_CMD_TIME_OUT: |
| 399 | printk(BIOS_DEBUG, "Time out when polling SendMrsCmd bit\n"); |
| 400 | break; |
| 401 | |
| 402 | case MEM_ERROR_SEND_ZQ_CMD_TIME_OUT: |
| 403 | printk(BIOS_DEBUG, "Time out when polling SendZQCmd bit\n"); |
| 404 | break; |
| 405 | |
| 406 | case MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT: |
| 407 | printk(BIOS_DEBUG, "Time out when polling DctExtraAccessDone bit\n"); |
| 408 | break; |
| 409 | |
| 410 | case MEM_ERROR_MEM_CLR_BUSY_TIME_OUT: |
| 411 | printk(BIOS_DEBUG, "Time out when polling MemClrBusy bit\n"); |
| 412 | break; |
| 413 | |
| 414 | case MEM_ERROR_MEM_CLEARED_TIME_OUT: |
| 415 | printk(BIOS_DEBUG, "Time out when polling MemCleared bit\n"); |
| 416 | break; |
| 417 | |
| 418 | case MEM_ERROR_FLUSH_WR_TIME_OUT: |
| 419 | printk(BIOS_DEBUG, "Time out when polling FlushWr bit\n"); |
| 420 | break; |
| 421 | |
| 422 | case MEM_ERROR_MAX_LAT_NO_WINDOW: |
| 423 | printk(BIOS_DEBUG, "Fail to find pass during Max Rd Latency training\n"); |
| 424 | break; |
| 425 | |
| 426 | case MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL: |
| 427 | printk(BIOS_DEBUG, "Fail to launch training code on an AP\n"); |
| 428 | break; |
| 429 | |
| 430 | case MEM_ERROR_PARALLEL_TRAINING_TIME_OUT: |
| 431 | printk(BIOS_DEBUG, "Fail to finish parallel training\n"); |
| 432 | break; |
| 433 | |
| 434 | case MEM_ERROR_NO_ADDRESS_MAPPING: |
| 435 | printk(BIOS_DEBUG, "No address mapping found for a dimm\n"); |
| 436 | break; |
| 437 | |
| 438 | case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT: |
| 439 | printk(BIOS_DEBUG, "There is no DQS receiver enable window and the value is equal to the largest value\n"); |
| 440 | break; |
| 441 | |
| 442 | case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE: |
| 443 | printk(BIOS_DEBUG, "Receive Enable value is too large and is 1 less than limit\n"); |
| 444 | break; |
| 445 | |
| 446 | case MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR: |
| 447 | printk(BIOS_DEBUG, "SPD Checksum error for NV_SPDCHK_RESTRT\n"); |
| 448 | break; |
| 449 | |
| 450 | case MEM_ERROR_NO_CHIPSELECT: |
| 451 | printk(BIOS_DEBUG, "No chipselects found\n"); |
| 452 | break; |
| 453 | |
| 454 | case MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM: |
| 455 | printk(BIOS_DEBUG, "Unbuffered dimm is not supported at 333MHz\n"); |
| 456 | break; |
| 457 | |
| 458 | case MEM_ERROR_WL_PRE_OUT_OF_RANGE: |
| 459 | printk(BIOS_DEBUG, "Returned PRE value during write levelizzation was out of range\n"); |
| 460 | break; |
| 461 | |
| 462 | case CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE: |
| 463 | printk(BIOS_DEBUG, "No heap is allocated for BrandId structure\n"); |
| 464 | break; |
| 465 | |
| 466 | case CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED: |
| 467 | printk(BIOS_DEBUG, "Unable to load micro code patch\n"); |
| 468 | break; |
| 469 | |
| 470 | case CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE: |
| 471 | printk(BIOS_DEBUG, "No heap is allocated for the Pstate structure\n"); |
| 472 | break; |
| 473 | |
| 474 | /* |
| 475 | case CPU_ERROR_PM_NB_PSTATE_MISMATCH: |
| 476 | printk(BIOS_DEBUG, "NB P-state indicated by Index was disabled due to mismatch between processors\n"); |
| 477 | break; |
| 478 | */ |
| 479 | |
| 480 | case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: |
| 481 | printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); |
| 482 | if ((event->EventInfo & 0x000000FF) == 0x04) { |
| 483 | printk(BIOS_DEBUG, "AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY\n"); |
| 484 | } else if ((event->EventInfo & 0x000000FF) == 0x05) { |
| 485 | printk(BIOS_DEBUG, "AGESA_START_ADDRESS_LESS_D0000\n"); |
| 486 | } else if ((event->EventInfo & 0x000000FF) == 0x06) { |
| 487 | printk(BIOS_DEBUG, "AGESA_THREE_CACHE_REGIONS_ABOVE_1MB\n"); |
| 488 | } else if ((event->EventInfo & 0x000000FF) == 0x07) { |
| 489 | printk(BIOS_DEBUG, "AGESA_DEALLOCATE_CACHE_REGIONS\n"); |
| 490 | } |
| 491 | printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", |
| 492 | (unsigned int)event->DataParam1, |
| 493 | (unsigned int)event->DataParam2, |
| 494 | (unsigned int)event->DataParam3); |
| 495 | break; |
| 496 | |
| 497 | case HT_EVENT_COH_NO_TOPOLOGY: |
| 498 | printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %x\n", |
| 499 | (unsigned int)event->DataParam1); |
| 500 | break; |
| 501 | |
| 502 | case HT_EVENT_NCOH_BUID_EXCEED: |
| 503 | printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%x Link%x Depth%x" |
| 504 | "Current BUID: %x, Unit Count: %x\n", |
| 505 | (unsigned int)event->DataParam1, |
| 506 | (unsigned int)event->DataParam2, |
| 507 | (unsigned int)event->DataParam3, |
| 508 | (unsigned int)event->DataParam4 >> 16, |
| 509 | (unsigned int)event->DataParam4 & 0x0000FFFF); |
| 510 | break; |
| 511 | |
| 512 | case HT_EVENT_NCOH_BUS_MAX_EXCEED: |
| 513 | printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %x Link %x Bus %x\n", |
| 514 | (unsigned int)event->DataParam1, |
| 515 | (unsigned int)event->DataParam2, |
| 516 | (unsigned int)event->DataParam3); |
| 517 | break; |
| 518 | |
| 519 | case HT_EVENT_NCOH_CFG_MAP_EXCEED: |
| 520 | printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %x Link %x\n", |
| 521 | (unsigned int)event->DataParam1, |
| 522 | (unsigned int)event->DataParam2); |
| 523 | break; |
| 524 | |
| 525 | case HT_EVENT_NCOH_DEVICE_FAILED: |
| 526 | printk(BIOS_DEBUG, "after assigning an IO Device an ID, it does not respond at the new ID" |
| 527 | "Socket %x Link %x Depth %x DeviceID %x\n", |
| 528 | (unsigned int)event->DataParam1, |
| 529 | (unsigned int)event->DataParam2, |
| 530 | (unsigned int)event->DataParam3, |
| 531 | (unsigned int)event->DataParam4); |
| 532 | default: |
| 533 | break; |
| 534 | } |
| 535 | } |
| 536 | /** |
| 537 | * |
| 538 | */ |
| 539 | static void agesa_critical(EVENT_PARAMS *event) |
| 540 | { |
| 541 | switch (event->EventInfo) { |
| 542 | case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3: |
| 543 | printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR3\n", |
| 544 | (unsigned int)event->DataParam1); |
| 545 | break; |
| 546 | |
| 547 | case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2: |
| 548 | printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR2\n", |
| 549 | (unsigned int)event->DataParam1); |
| 550 | break; |
| 551 | |
| 552 | case MEM_ERROR_UNSUPPORTED_DIMM_CONFIG: |
| 553 | printk(BIOS_DEBUG, "Socket: %x, Dimm population is not supported\n", |
| 554 | (unsigned int)event->DataParam1); |
| 555 | break; |
| 556 | |
| 557 | case HT_EVENT_COH_PROCESSOR_TYPE_MIX: |
| 558 | printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n", |
| 559 | (unsigned int)event->DataParam1, |
| 560 | (unsigned int)event->DataParam2, |
| 561 | (unsigned int)event->DataParam3); |
| 562 | break; |
| 563 | |
| 564 | case HT_EVENT_COH_MPCAP_MISMATCH: |
| 565 | printk(BIOS_DEBUG, "Socket %x Link %x MpCap %x TotalSockets %x, HT_EVENT_COH_MPCAP_MISMATCH\n", |
| 566 | (unsigned int)event->DataParam1, |
| 567 | (unsigned int)event->DataParam2, |
| 568 | (unsigned int)event->DataParam3, |
| 569 | (unsigned int)event->DataParam4); |
| 570 | default: |
| 571 | break; |
| 572 | } |
| 573 | } |
| 574 | |
| 575 | /** |
| 576 | * |
| 577 | */ |
| 578 | static void agesa_fatal(EVENT_PARAMS *event) |
| 579 | { |
| 580 | |
| 581 | switch (event->EventInfo >> 24) { |
| 582 | case 0x04: |
| 583 | printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", |
| 584 | (unsigned int)event->DataParam1, |
| 585 | (unsigned int)event->DataParam2, |
| 586 | (unsigned int)event->DataParam3); |
| 587 | break; |
| 588 | |
| 589 | case 0x08: |
| 590 | printk(BIOS_DEBUG, "Processor: "); |
| 591 | break; |
| 592 | |
| 593 | case 0x10: |
| 594 | printk(BIOS_DEBUG, "Hyper Transport: "); |
| 595 | break; |
| 596 | |
| 597 | default: |
| 598 | break; |
| 599 | } |
| 600 | |
| 601 | switch (event->EventInfo) { |
| 602 | case MEM_ERROR_MINIMUM_MODE: |
| 603 | printk(BIOS_DEBUG, "Running in minimum mode\n"); |
| 604 | break; |
| 605 | |
| 606 | case MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM: |
| 607 | printk(BIOS_DEBUG, "DIMM modules are missmatched\n"); |
| 608 | break; |
| 609 | |
| 610 | case MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM: |
| 611 | printk(BIOS_DEBUG, "No DIMMs have been foun\n"); |
| 612 | break; |
| 613 | |
| 614 | case MEM_ERROR_MISMATCH_DIMM_CLOCKS: |
| 615 | printk(BIOS_DEBUG, "DIMM clocks miss-matched\n"); |
| 616 | break; |
| 617 | |
| 618 | case MEM_ERROR_NO_CYC_TIME: |
| 619 | printk(BIOS_DEBUG, "No cycle time found\n"); |
| 620 | break; |
| 621 | case MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS: |
| 622 | printk(BIOS_DEBUG, "Heap allocation error with dynamic storing of trained timings\n"); |
| 623 | break; |
| 624 | |
| 625 | case MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs: |
| 626 | printk(BIOS_DEBUG, "Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT\n"); |
| 627 | break; |
| 628 | |
| 629 | case MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV: |
| 630 | printk(BIOS_DEBUG, "Heap allocation error with REMOTE_TRAINING_ENV\n"); |
| 631 | break; |
| 632 | |
| 633 | case MEM_ERROR_HEAP_ALLOCATE_FOR_SPD: |
| 634 | printk(BIOS_DEBUG, "Heap allocation error for SPD data\n"); |
| 635 | break; |
| 636 | |
| 637 | case MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA: |
| 638 | printk(BIOS_DEBUG, "Heap allocation error for RECEIVED_DATA during parallel training\n"); |
| 639 | break; |
| 640 | |
| 641 | case MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS: |
| 642 | printk(BIOS_DEBUG, "Heap allocation error for S3 \"SPECIAL_CASE_REGISTER\"\n"); |
| 643 | break; |
| 644 | |
| 645 | case MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA: |
| 646 | printk(BIOS_DEBUG, "Heap allocation error for Training Data\n"); |
| 647 | break; |
| 648 | |
| 649 | case MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK: |
| 650 | printk(BIOS_DEBUG, "Heap allocation error for DIMM Identify \"MEM_NB_BLOCK\"\n"); |
| 651 | break; |
| 652 | |
| 653 | case MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM: |
| 654 | printk(BIOS_DEBUG, "No Constructor for DIMM Identify\n"); |
| 655 | break; |
| 656 | |
| 657 | case MEM_ERROR_VDDIO_UNSUPPORTED: |
| 658 | printk(BIOS_DEBUG, "VDDIO of the dimms on the board is not supported\n"); |
| 659 | break; |
| 660 | |
| 661 | case CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT: |
| 662 | printk(BIOS_DEBUG, "Socket: %x, All PStates exceeded the motherboard current limit on specified socket\n", |
| 663 | (unsigned int)event->DataParam1); |
| 664 | break; |
| 665 | |
| 666 | default: |
| 667 | break; |
| 668 | } |
| 669 | } |
| 670 | |
| 671 | /** |
| 672 | * |
| 673 | * Interprte the agesa event log to an user readable string |
| 674 | */ |
| 675 | static void interpret_agesa_eventlog(EVENT_PARAMS *event) |
| 676 | { |
| 677 | switch (event->EventClass) { |
| 678 | case AGESA_BOUNDS_CHK: |
| 679 | agesa_bound_check(event); |
| 680 | break; |
| 681 | |
| 682 | case AGESA_ALERT: |
| 683 | agesa_alert(event); |
| 684 | break; |
| 685 | |
| 686 | case AGESA_WARNING: |
| 687 | agesa_warning(event); |
| 688 | break; |
| 689 | |
| 690 | case AGESA_ERROR: |
| 691 | agesa_error(event); |
| 692 | break; |
| 693 | |
| 694 | case AGESA_CRITICAL: |
| 695 | agesa_critical(event); |
| 696 | break; |
| 697 | |
| 698 | case AGESA_FATAL: |
| 699 | agesa_fatal(event); |
| 700 | break; |
| 701 | |
| 702 | default: |
| 703 | break; |
| 704 | } |
| 705 | } |
| 706 | #endif |
| 707 | |
Kyösti Mälkki | 1aa35c6 | 2014-10-21 14:19:04 +0300 | [diff] [blame] | 708 | static void amd_readeventlog(AMD_CONFIG_PARAMS *StdHeader) |
Kyösti Mälkki | e68f4ff | 2014-10-22 15:53:34 +0300 | [diff] [blame] | 709 | { |
Kyösti Mälkki | e68f4ff | 2014-10-22 15:53:34 +0300 | [diff] [blame] | 710 | EVENT_PARAMS AmdEventParams; |
| 711 | |
Kyösti Mälkki | 1aa35c6 | 2014-10-21 14:19:04 +0300 | [diff] [blame] | 712 | memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); |
Kyösti Mälkki | e68f4ff | 2014-10-22 15:53:34 +0300 | [diff] [blame] | 713 | |
| 714 | AmdEventParams.StdHeader.AltImageBasePtr = 0; |
Kyösti Mälkki | 82860f8 | 2015-10-30 23:38:40 +0200 | [diff] [blame] | 715 | AmdEventParams.StdHeader.CalloutPtr = &GetBiosCallout; |
Kyösti Mälkki | e68f4ff | 2014-10-22 15:53:34 +0300 | [diff] [blame] | 716 | AmdEventParams.StdHeader.Func = 0; |
| 717 | AmdEventParams.StdHeader.ImageBasePtr = 0; |
Kyösti Mälkki | 1aa35c6 | 2014-10-21 14:19:04 +0300 | [diff] [blame] | 718 | AmdEventParams.StdHeader.HeapStatus = StdHeader->HeapStatus; |
| 719 | |
| 720 | AmdReadEventLog(&AmdEventParams); |
Kyösti Mälkki | e68f4ff | 2014-10-22 15:53:34 +0300 | [diff] [blame] | 721 | while (AmdEventParams.EventClass != 0) { |
| 722 | printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", |
| 723 | (unsigned int)AmdEventParams.EventClass, |
| 724 | (unsigned int)AmdEventParams.EventInfo); |
| 725 | printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n", |
| 726 | (unsigned int)AmdEventParams.DataParam1, |
| 727 | (unsigned int)AmdEventParams.DataParam2); |
| 728 | printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n", |
| 729 | (unsigned int)AmdEventParams.DataParam3, |
| 730 | (unsigned int)AmdEventParams.DataParam4); |
Kyösti Mälkki | 1aa35c6 | 2014-10-21 14:19:04 +0300 | [diff] [blame] | 731 | AmdReadEventLog(&AmdEventParams); |
Kyösti Mälkki | e68f4ff | 2014-10-22 15:53:34 +0300 | [diff] [blame] | 732 | } |
Kyösti Mälkki | 1aa35c6 | 2014-10-21 14:19:04 +0300 | [diff] [blame] | 733 | } |
Kyösti Mälkki | e68f4ff | 2014-10-22 15:53:34 +0300 | [diff] [blame] | 734 | |
Kyösti Mälkki | 1aa35c6 | 2014-10-21 14:19:04 +0300 | [diff] [blame] | 735 | |
| 736 | void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func) |
| 737 | { |
| 738 | printk(BIOS_DEBUG, "%s() returned %s\n", func, decodeAGESA_STATUS(ret)); |
| 739 | if (ret != AGESA_SUCCESS) |
| 740 | amd_readeventlog(StdHeader); |
Kyösti Mälkki | e68f4ff | 2014-10-22 15:53:34 +0300 | [diff] [blame] | 741 | } |