Siyuan Wang | 1ee8b45 | 2012-09-07 19:20:02 +0800 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
Siyuan Wang | 1ee8b45 | 2012-09-07 19:20:02 +0800 | [diff] [blame] | 15 | chip northbridge/amd/agesa/family15/root_complex |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 16 | device cpu_cluster 0 on |
Siyuan Wang | 1ee8b45 | 2012-09-07 19:20:02 +0800 | [diff] [blame] | 17 | chip cpu/amd/agesa/family15 |
Siyuan Wang | 3d4762d | 2013-01-04 13:07:49 +0800 | [diff] [blame] | 18 | device lapic 0x10 on end |
Siyuan Wang | 1ee8b45 | 2012-09-07 19:20:02 +0800 | [diff] [blame] | 19 | end |
| 20 | end |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 21 | device domain 0 on |
Siyuan Wang | 1ee8b45 | 2012-09-07 19:20:02 +0800 | [diff] [blame] | 22 | subsystemid 0x15d9 0xab11 inherit #Tyan |
| 23 | chip northbridge/amd/agesa/family15 # CPU side of HT root complex |
| 24 | device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology |
| 25 | chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex |
| 26 | device pci 0.0 on end # HT Root Complex 0x9600 |
| 27 | device pci 0.1 off end # CLKCONFIG |
| 28 | device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16 |
| 29 | device pci 3.0 off end # GPP1 Port1 |
| 30 | device pci 4.0 on end # GPP3a Port0 x4 SAS |
| 31 | device pci 5.0 on end # GPP3a Port1 |
| 32 | device pci 6.0 on end # GPP3a Port2 |
| 33 | device pci 7.0 on end # GPP3a Port3 |
| 34 | device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time |
| 35 | device pci 9.0 on end # GPP3a Port4 x1 NC |
| 36 | device pci a.0 on end # GPP3a Port5 x1 NC |
| 37 | device pci b.0 on end # GPP2 Port0 (Not for sr5650) |
| 38 | device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) |
| 39 | device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 |
| 40 | register "gpp1_configuration" = "0" # Configuration 16:0 default |
| 41 | register "gpp2_configuration" = "0" # Configuration 8:8 |
| 42 | register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 |
| 43 | register "port_enable" = "0x3ef6" |
| 44 | end #northbridge/amd/cimx/rd890 |
| 45 | chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus |
| 46 | device pci 11.0 on end # SATA |
| 47 | device pci 12.0 on end # USB1 |
| 48 | device pci 12.1 on end # USB1 |
| 49 | device pci 12.2 on end # USB1 |
| 50 | device pci 13.0 on end # USB2 |
| 51 | device pci 13.1 on end # USB2 |
| 52 | device pci 13.2 on end # USB2 |
| 53 | device pci 14.0 on end # SM |
| 54 | device pci 14.1 off end # IDE 0x439c |
| 55 | device pci 14.2 off end # HDA 0x4383, s8226 not have codec. |
| 56 | device pci 14.3 on # LPC 0x439d |
| 57 | chip superio/winbond/w83627dhg |
| 58 | device pnp 2e.0 off # Floppy |
| 59 | io 0x60 = 0x3f0 |
| 60 | irq 0x70 = 6 |
| 61 | drq 0x74 = 2 |
| 62 | end |
| 63 | device pnp 2e.1 off # Parallel Port |
| 64 | io 0x60 = 0x378 |
| 65 | irq 0x70 = 7 |
| 66 | end |
| 67 | device pnp 2e.2 on # Com1 |
| 68 | io 0x60 = 0x3f8 |
| 69 | irq 0x70 = 4 |
| 70 | end |
| 71 | device pnp 2e.3 on # Com2 |
| 72 | io 0x60 = 0x2f8 |
| 73 | irq 0x70 = 3 |
| 74 | end |
| 75 | ## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS## |
| 76 | device pnp 2e.5 on # PS/2 keyboard & mouse |
| 77 | io 0x60 = 0x60 |
| 78 | io 0x62 = 0x64 |
| 79 | irq 0x70 = 0x01 #keyboard |
| 80 | irq 0x72 = 0x0C #mouse |
| 81 | end |
| 82 | device pnp 2e.6 off # SPI |
| 83 | end |
| 84 | device pnp 2e.307 off # GPIO6 |
| 85 | end |
| 86 | device pnp 2e.8 off # WDTO#, PLED |
| 87 | end |
| 88 | device pnp 2e.009 off # GPIO2 |
| 89 | end |
| 90 | device pnp 2e.109 off # GPIO3 |
| 91 | end |
| 92 | device pnp 2e.209 off # GPIO4 |
| 93 | end |
| 94 | device pnp 2e.309 off # GPIO5 |
| 95 | end |
| 96 | device pnp 2e.a off # ACPI |
| 97 | end |
| 98 | device pnp 2e.b off # HWM |
| 99 | io 0x60 = 0x290 |
| 100 | end |
| 101 | device pnp 2e.c off # PECI, SST |
| 102 | end |
| 103 | end #superio/winbond/w83627dhg |
| 104 | chip drivers/i2c/w83795 |
Timothy Pearson | d59dc45 | 2015-10-22 02:53:39 -0500 | [diff] [blame] | 105 | register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 |
| 106 | register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions |
| 107 | register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 |
| 108 | register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 |
| 109 | register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 |
| 110 | register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 |
| 111 | register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT |
| 112 | register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) |
| 113 | register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) |
| 114 | register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) |
| 115 | register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) |
| 116 | register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) |
| 117 | register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) |
| 118 | register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 |
| 119 | register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 |
| 120 | register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 |
| 121 | register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 |
| 122 | register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 |
| 123 | register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 |
| 124 | register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C |
| 125 | register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C |
| 126 | register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C |
| 127 | register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C |
| 128 | register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C |
| 129 | register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C |
| 130 | register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C |
| 131 | register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C |
| 132 | register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C |
| 133 | register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C |
| 134 | register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C |
| 135 | register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C |
| 136 | register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C |
| 137 | register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C |
| 138 | register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C |
| 139 | register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C |
| 140 | register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C |
| 141 | register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C |
| 142 | register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C |
| 143 | register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C |
| 144 | register "fan1_nonstop" = "7" # Set Fan 1 minimum speed |
| 145 | register "fan2_nonstop" = "7" # Set Fan 2 minimum speed |
| 146 | register "fan3_nonstop" = "7" # Set Fan 3 minimum speed |
| 147 | register "fan4_nonstop" = "7" # Set Fan 4 minimum speed |
| 148 | register "fan5_nonstop" = "7" # Set Fan 5 minimum speed |
| 149 | register "fan6_nonstop" = "7" # Set Fan 6 minimum speed |
| 150 | register "fan7_nonstop" = "7" # Set Fan 7 minimum speed |
| 151 | register "fan8_nonstop" = "7" # Set Fan 8 minimum speed |
| 152 | register "default_speed" = "100" # All fans to full speed on power up |
| 153 | register "fan1_duty" = "100" # Fan 1 to full speed |
| 154 | register "fan2_duty" = "100" # Fan 2 to full speed |
| 155 | register "fan3_duty" = "100" # Fan 3 to full speed |
| 156 | register "fan4_duty" = "100" # Fan 4 to full speed |
| 157 | register "fan5_duty" = "100" # Fan 5 to full speed |
| 158 | register "fan6_duty" = "100" # Fan 6 to full speed |
| 159 | register "fan7_duty" = "100" # Fan 7 to full speed |
| 160 | register "fan8_duty" = "100" # Fan 8 to full speed |
| 161 | register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V |
| 162 | register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V |
| 163 | register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V |
| 164 | register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V |
| 165 | register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V |
| 166 | register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V |
| 167 | register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V |
| 168 | register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V |
| 169 | register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V |
| 170 | register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V |
| 171 | register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V |
| 172 | register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V |
| 173 | register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V |
| 174 | register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V |
| 175 | register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V |
| 176 | register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V |
| 177 | register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V |
| 178 | register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V |
| 179 | register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V |
| 180 | register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V |
| 181 | register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V |
| 182 | register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V |
| 183 | register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V |
| 184 | register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V |
| 185 | register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V |
| 186 | register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V |
| 187 | register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V |
| 188 | register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V |
| 189 | register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V |
| 190 | register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V |
| 191 | register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V |
| 192 | register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V |
| 193 | register "smbus_aux" = "0" # Device located on primary SMBUS |
Siyuan Wang | 1ee8b45 | 2012-09-07 19:20:02 +0800 | [diff] [blame] | 194 | device pnp 5e on #hwm |
| 195 | end |
| 196 | end #drivers/i2c/w83795 |
| 197 | end # LPC |
| 198 | device pci 14.4 on end # PCI 0x4384 |
| 199 | device pci 14.5 on end # USB 3 |
| 200 | register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE |
| 201 | end # southbridge/amd/cimx/sb700 |
| 202 | end # device pci 18.0 |
| 203 | |
| 204 | device pci 18.1 on end |
| 205 | device pci 18.2 on end |
| 206 | device pci 18.3 on end |
| 207 | device pci 18.4 on end |
| 208 | device pci 18.5 on end #f15 |
Kimarie Hoot | b37ec54 | 2013-03-08 15:31:49 -0700 | [diff] [blame] | 209 | |
| 210 | register "spdAddrLookup" = " |
| 211 | { |
| 212 | { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 0 |
| 213 | { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 1 |
| 214 | }" |
Siyuan Wang | 1ee8b45 | 2012-09-07 19:20:02 +0800 | [diff] [blame] | 215 | end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 216 | end #domain |
Siyuan Wang | 1ee8b45 | 2012-09-07 19:20:02 +0800 | [diff] [blame] | 217 | end #northbridge/amd/agesa/family15/root_complex |