Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <stdint.h> |
| 19 | #include <string.h> |
| 20 | #include <arch/io.h> |
Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 21 | #include <device/pci_def.h> |
| 22 | #include <device/pnp_def.h> |
| 23 | #include <cpu/x86/lapic.h> |
| 24 | #include <lib.h> |
| 25 | #include <console/console.h> |
| 26 | #include <cpu/x86/bist.h> |
Edward O'Callaghan | 8199809 | 2014-04-28 18:07:33 +1000 | [diff] [blame] | 27 | #include <superio/winbond/common/winbond.h> |
| 28 | #include <superio/winbond/w83627hf/w83627hf.h> |
Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 29 | #include <northbridge/intel/i5000/raminit.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 30 | #include <northbridge/intel/i3100/i3100.h> |
| 31 | #include <southbridge/intel/i3100/i3100.h> |
Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 32 | #include <southbridge/intel/i3100/early_smbus.c> |
| 33 | |
| 34 | #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) |
| 35 | #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) |
| 36 | |
| 37 | #define RCBA_RPC 0x0224 /* 32 bit */ |
| 38 | #define RCBA_HPTC 0x3404 /* 32 bit */ |
| 39 | #define RCBA_GCS 0x3410 /* 32 bit */ |
| 40 | #define RCBA_FD 0x3418 /* 32 bit */ |
| 41 | |
Edward O'Callaghan | 8199809 | 2014-04-28 18:07:33 +1000 | [diff] [blame] | 42 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| 43 | |
Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 44 | static void early_config(void) |
| 45 | { |
| 46 | u32 gcs, rpc, fd; |
| 47 | |
| 48 | /* Enable RCBA */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 49 | pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 50 | |
| 51 | /* Disable watchdog */ |
| 52 | gcs = read32(DEFAULT_RCBA + RCBA_GCS); |
| 53 | gcs |= (1 << 5); /* No reset */ |
| 54 | write32(DEFAULT_RCBA + RCBA_GCS, gcs); |
| 55 | |
| 56 | /* Configure PCIe port B as 4x */ |
| 57 | rpc = read32(DEFAULT_RCBA + RCBA_RPC); |
| 58 | rpc |= (3 << 0); |
| 59 | write32(DEFAULT_RCBA + RCBA_RPC, rpc); |
| 60 | |
| 61 | /* Disable Modem, Audio, PCIe ports 2/3/4 */ |
| 62 | fd = read32(DEFAULT_RCBA + RCBA_FD); |
| 63 | fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5); |
| 64 | write32(DEFAULT_RCBA + RCBA_FD, fd); |
| 65 | |
| 66 | /* Enable HPET */ |
| 67 | write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7)); |
| 68 | |
| 69 | /* Setup sata mode */ |
| 70 | pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40); |
| 71 | } |
| 72 | |
| 73 | #define DEFAULT_GPIOBASE 0x1180 |
| 74 | static void setup_gpio(void) |
| 75 | { |
| 76 | pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1); |
| 77 | pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4)); |
| 78 | |
| 79 | outl(0xff0c79cf, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ |
| 80 | outl(0xe700ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ |
| 81 | outl(0x65b70000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 82 | outl(0x0000718a, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ |
| 83 | outl(0x00000106, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ |
| 84 | outl(0x00000301, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ |
| 85 | outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ |
| 86 | } |
| 87 | |
| 88 | static void i5000_lpc_config(void) |
| 89 | { |
| 90 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); |
| 91 | } |
| 92 | |
| 93 | int mainboard_set_fbd_clock(int speed) |
| 94 | { |
| 95 | switch(speed) { |
| 96 | case 533: |
| 97 | smbus_write_byte(0x6f, 0x80, 0x21); |
| 98 | return 0; |
| 99 | case 667: |
| 100 | smbus_write_byte(0x6f, 0x80, 0x23); |
| 101 | return 0; |
| 102 | default: |
| 103 | printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed); |
| 104 | die(""); |
| 105 | return -1; |
| 106 | } |
| 107 | } |
| 108 | |
Aaron Durbin | a0a3727 | 2014-08-14 08:35:11 -0500 | [diff] [blame] | 109 | #include <cpu/intel/romstage.h> |
Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 110 | void main(unsigned long bist) |
| 111 | { |
| 112 | if (bist == 0) |
| 113 | enable_lapic(); |
| 114 | |
| 115 | i5000_lpc_config(); |
| 116 | |
Edward O'Callaghan | 8199809 | 2014-04-28 18:07:33 +1000 | [diff] [blame] | 117 | winbond_enable_serial(SERIAL_DEV, 0x3f8); |
Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 118 | console_init(); |
| 119 | |
| 120 | /* Halt if there was a built in self test failure */ |
| 121 | report_bist_failure(bist); |
| 122 | |
| 123 | early_config(); |
| 124 | |
| 125 | setup_gpio(); |
| 126 | |
| 127 | enable_smbus(); |
| 128 | |
Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 129 | outb(0x07, 0x11b8); |
| 130 | |
| 131 | /* These are smbus write captured with serialice. They |
| 132 | seem to setup the clock generator */ |
| 133 | |
| 134 | smbus_write_byte(0x6f, 0x88, 0x1f); |
| 135 | smbus_write_byte(0x6f, 0x81, 0xff); |
| 136 | smbus_write_byte(0x6f, 0x82, 0xff); |
| 137 | smbus_write_byte(0x6f, 0x80, 0x23); |
| 138 | |
| 139 | outb(0x03, 0x11b8); |
| 140 | outb(0x01, 0x11b8); |
| 141 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 142 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1); |
Sven Schnelle | 72f35a6 | 2012-06-20 14:56:46 +0200 | [diff] [blame] | 143 | i5000_fbdimm_init(); |
| 144 | smbus_write_byte(0x69, 0x01, 0x01); |
| 145 | } |