Siyuan Wang | 8ff97b2 | 2012-10-28 18:19:38 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Siyuan Wang | 8ff97b2 | 2012-10-28 18:19:38 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <arch/io.h> |
| 20 | #include <boot/tables.h> |
| 21 | #include <cpu/x86/msr.h> |
| 22 | #include <cpu/amd/mtrr.h> |
| 23 | #include <device/pci_def.h> |
| 24 | #include <NbPlatform.h> |
| 25 | #include "chip.h" |
| 26 | |
| 27 | void set_pcie_dereset(void *nbconfig); |
| 28 | void set_pcie_reset(void *nbconfig); |
| 29 | |
| 30 | /** |
| 31 | * |
| 32 | */ |
| 33 | void set_pcie_reset(void *nbconfig) |
| 34 | { |
| 35 | } |
| 36 | |
| 37 | /** |
| 38 | * Mainboard specific RD890 CIMx callback |
| 39 | * Release Resets to PCIe Links |
| 40 | * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie |
| 41 | */ |
| 42 | void set_pcie_dereset(void *nbconfig) |
| 43 | { |
| 44 | //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); |
| 45 | u32 i; |
| 46 | u32 val; |
| 47 | u32 nb_addr; |
| 48 | |
| 49 | val = 0x00000007UL; |
| 50 | AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig; |
| 51 | for (i = 0; i < MAX_NB_COUNT; i ++) { |
| 52 | nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX; |
| 53 | LibNbPciIndexRMW(nb_addr, |
| 54 | NB_HTIU_REGA8, |
| 55 | AccessS3SaveWidth32, |
| 56 | ~val, |
| 57 | val, |
| 58 | &(pConfig->Northbridges[i])); |
| 59 | } |
| 60 | } |
| 61 | |
| 62 | |
| 63 | /************************************************* |
| 64 | * enable the dedicated function in h8scm board. |
| 65 | *************************************************/ |
Paul Menzel | 528640d | 2013-02-23 21:31:23 +0100 | [diff] [blame] | 66 | static void mainboard_enable(device_t dev) |
Siyuan Wang | 8ff97b2 | 2012-10-28 18:19:38 +0800 | [diff] [blame] | 67 | { |
| 68 | printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); |
| 69 | } |
| 70 | |
Siyuan Wang | 8ff97b2 | 2012-10-28 18:19:38 +0800 | [diff] [blame] | 71 | struct chip_operations mainboard_ops = { |
Paul Menzel | 528640d | 2013-02-23 21:31:23 +0100 | [diff] [blame] | 72 | .enable_dev = mainboard_enable, |
Siyuan Wang | 8ff97b2 | 2012-10-28 18:19:38 +0800 | [diff] [blame] | 73 | }; |