Siyuan Wang | 8ff97b2 | 2012-10-28 18:19:38 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Siyuan Wang | 8ff97b2 | 2012-10-28 18:19:38 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
Edward O'Callaghan | d5339ae | 2014-07-07 19:58:53 +1000 | [diff] [blame] | 16 | #include <stdlib.h> |
| 17 | |
Siyuan Wang | 8ff97b2 | 2012-10-28 18:19:38 +0800 | [diff] [blame] | 18 | #include "AGESA.h" |
| 19 | #include "CommonReturns.h" |
| 20 | #include "AdvancedApi.h" |
| 21 | #include <PlatformMemoryConfiguration.h> |
| 22 | #include "Filecode.h" |
| 23 | #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE |
| 24 | //#define OPTION_HW_DQS_REC_EN_TRAINING TRUE |
| 25 | /* AGESA will check the OEM configuration during preprocessing stage, |
| 26 | * coreboot enable -Wundef option, so we should make sure we have all contanstand defined |
| 27 | */ |
| 28 | /* MEMORY_BUS_SPEED */ |
Elyes HAOUAS | 4d529da | 2014-07-22 19:03:14 +0200 | [diff] [blame] | 29 | #define DDR400_FREQUENCY 200 ///< DDR 400 |
| 30 | #define DDR533_FREQUENCY 266 ///< DDR 533 |
| 31 | #define DDR667_FREQUENCY 333 ///< DDR 667 |
| 32 | #define DDR800_FREQUENCY 400 ///< DDR 800 |
| 33 | #define DDR1066_FREQUENCY 533 ///< DDR 1066 |
| 34 | #define DDR1333_FREQUENCY 667 ///< DDR 1333 |
| 35 | #define DDR1600_FREQUENCY 800 ///< DDR 1600 |
| 36 | #define DDR1866_FREQUENCY 933 ///< DDR 1866 |
| 37 | #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency |
Siyuan Wang | 8ff97b2 | 2012-10-28 18:19:38 +0800 | [diff] [blame] | 38 | |
| 39 | /* QUANDRANK_TYPE */ |
| 40 | #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM |
| 41 | #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM |
| 42 | |
| 43 | /* USER_MEMORY_TIMING_MODE */ |
| 44 | #define TIMING_MODE_AUTO 0 ///< Use best rate possible |
| 45 | #define TIMING_MODE_LIMITED 1 ///< Set user top limit |
| 46 | #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed |
| 47 | |
| 48 | /* POWER_DOWN_MODE */ |
| 49 | #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode |
| 50 | #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode |
| 51 | |
| 52 | /* User makes option selections here |
| 53 | * Comment out the items wanted to be included in the build. |
| 54 | * Uncomment those items you with to REMOVE from the build. |
| 55 | */ |
| 56 | //#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE |
| 57 | //#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE |
| 58 | //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE |
| 59 | //#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE |
| 60 | //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE |
| 61 | //#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE |
| 62 | //#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE |
| 63 | //#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE |
| 64 | #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE |
| 65 | //#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE |
| 66 | //#define BLDOPT_REMOVE_ACPI_PSTATES TRUE |
| 67 | //#define BLDOPT_REMOVE_SRAT TRUE |
| 68 | //#define BLDOPT_REMOVE_SLIT TRUE |
| 69 | //#define BLDOPT_REMOVE_WHEA TRUE |
| 70 | //#define BLDOPT_REMOVE_DMI TRUE |
| 71 | |
| 72 | /*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */ |
| 73 | #define BLDOPT_REMOVE_EARLY_SAMPLES FALSE |
| 74 | |
| 75 | //#define BLDOPT_REMOVE_HT_ASSIST TRUE |
| 76 | //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE |
| 77 | //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE |
| 78 | //#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE |
| 79 | //#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE |
| 80 | //#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE |
| 81 | //#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE |
| 82 | |
| 83 | /* Build configuration values here. |
| 84 | */ |
| 85 | #define BLDCFG_VRM_CURRENT_LIMIT 120000 |
| 86 | #define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 |
| 87 | #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 |
| 88 | #define BLDCFG_PLAT_NUM_IO_APICS 3 |
| 89 | #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST |
| 90 | #define BLDCFG_MEM_INIT_PSTATE 0 |
| 91 | #define BLDCFG_AMD_PSTATE_CAP_VALUE 0 |
| 92 | |
| 93 | #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER |
| 94 | |
| 95 | #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY//1600 |
| 96 | #define BLDCFG_MEMORY_MODE_UNGANGED TRUE |
| 97 | #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE |
| 98 | #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED |
| 99 | #define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE |
| 100 | #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE |
| 101 | #define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE |
| 102 | #define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE |
| 103 | #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE |
| 104 | #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE |
| 105 | #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE//TRUE |
| 106 | #define BLDCFG_MEMORY_POWER_DOWN FALSE |
| 107 | #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL |
| 108 | #define BLDCFG_ONLINE_SPARE FALSE |
| 109 | #define BLDCFG_BANK_SWIZZLE TRUE |
| 110 | #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO |
| 111 | #define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY //DDR800_FREQUENCY |
| 112 | #define BLDCFG_DQS_TRAINING_CONTROL TRUE |
| 113 | #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE |
| 114 | #define BLDCFG_USE_BURST_MODE FALSE |
| 115 | #define BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE |
| 116 | #define BLDCFG_ENABLE_ECC_FEATURE TRUE |
| 117 | #define BLDCFG_ECC_REDIRECTION FALSE |
| 118 | #define BLDCFG_SCRUB_IC_RATE 0 |
| 119 | #define BLDCFG_ECC_SYNC_FLOOD TRUE |
| 120 | #define BLDCFG_ECC_SYMBOL_SIZE 4 |
| 121 | |
| 122 | #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS |
| 123 | #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER |
| 124 | |
| 125 | /** |
| 126 | * Enable Message Based C1e CPU feature in multi-socket systems. |
| 127 | * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value, |
| 128 | * else the feature cannot be enabled. |
| 129 | */ |
| 130 | #define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased |
| 131 | #define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO |
| 132 | //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 |
| 133 | //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 |
| 134 | |
| 135 | #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 |
| 136 | #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 |
| 137 | #define BLDCFG_1GB_ALIGN FALSE |
| 138 | //#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' |
| 139 | //#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' |
| 140 | // |
| 141 | |
| 142 | // Select the platform control flow mode for performance tuning. |
| 143 | #define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm |
| 144 | |
| 145 | /** |
| 146 | * Enable the probe filtering performance tuning feature. |
| 147 | * The probe filter provides filtering of broadcast probes to |
| 148 | * improve link bandwidth and performance for multi- node systems. |
| 149 | * |
| 150 | * This feature may interact with other performance features. |
| 151 | * TRUE -Enable the feature (default) if supported by all processors, |
| 152 | * based on revision and presence of L3 cache. |
| 153 | * The feature is not enabled if there are no coherent HT links. |
| 154 | * FALSE -Do not enable the feature regardless of the configuration. |
| 155 | */ |
| 156 | //TODO enable it, |
| 157 | //but AGESA set PFMode = 0; //PF Disable, HW never set PFInitDone |
| 158 | //hang in F10HtAssistInit() do{...} while(PFInitDone != 1) |
| 159 | #define BLDCFG_USE_HT_ASSIST FALSE |
| 160 | |
| 161 | /** |
| 162 | * The socket and link match values are platform specific |
| 163 | */ |
| 164 | CONST MANUAL_BUID_SWAP_LIST ROMDATA h8scm_manual_swaplist[2] = |
| 165 | { |
| 166 | { |
| 167 | /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ |
| 168 | HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, |
| 169 | |
| 170 | { //BUID Swap List |
| 171 | { //BUID Swaps |
| 172 | /* Each Non-coherent chain may have a list of device swaps, |
| 173 | * Each item specify a device will be swap from its current id to a new one |
| 174 | */ |
| 175 | /* FromID 0x00 is the chain with the southbridge */ |
| 176 | /* 'Move' device zero to device zero, All others are non applicable */ |
| 177 | {0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, |
| 178 | {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, |
| 179 | {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, |
| 180 | {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, |
| 181 | {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, |
| 182 | {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, |
| 183 | {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, |
| 184 | {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, |
| 185 | }, |
| 186 | |
| 187 | { //The ordered final BUIDs |
| 188 | /* Specify the final BUID to be zero, All others are non applicable */ |
| 189 | 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, |
| 190 | 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, |
| 191 | 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, |
| 192 | 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, |
| 193 | } |
| 194 | } |
| 195 | }, |
| 196 | |
| 197 | /* The 2nd element in the array merely terminates the list */ |
| 198 | { |
| 199 | HT_LIST_TERMINAL, |
| 200 | } |
| 201 | }; |
| 202 | |
Kyösti Mälkki | 225da64 | 2015-02-04 13:46:12 +0200 | [diff] [blame] | 203 | #define HYPERTRANSPORT_V31_SUPPORT 1 |
| 204 | |
| 205 | #if HYPERTRANSPORT_V31_SUPPORT |
Siyuan Wang | 8ff97b2 | 2012-10-28 18:19:38 +0800 | [diff] [blame] | 206 | /** |
| 207 | * The socket and link match values are platform specific |
| 208 | * |
| 209 | */ |
| 210 | CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8scm_cpu2cpu_limit_list[2] = |
| 211 | { |
| 212 | { |
| 213 | /* On the reference platform, these settings apply to all coherent links */ |
| 214 | HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, |
| 215 | |
| 216 | /* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */ |
| 217 | HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, |
| 218 | }, |
| 219 | |
| 220 | /* The 2nd element in the array merely terminates the list */ |
| 221 | { |
| 222 | HT_LIST_TERMINAL, |
| 223 | } |
| 224 | }; |
| 225 | |
| 226 | CONST IO_PCB_LIMITS ROMDATA h8scm_io_limit_list[2] = |
| 227 | { |
| 228 | { |
| 229 | /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ |
| 230 | HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, |
| 231 | |
| 232 | /* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */ |
| 233 | HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, //Actually IO hub only support 2600M MAX |
| 234 | }, |
| 235 | |
| 236 | /* The 2nd element in the array merely terminates the list */ |
| 237 | { |
| 238 | HT_LIST_TERMINAL, |
| 239 | } |
| 240 | }; |
Kyösti Mälkki | 225da64 | 2015-02-04 13:46:12 +0200 | [diff] [blame] | 241 | #else /* HYPERTRANSPORT_V31_SUPPORT == 0 */ |
Siyuan Wang | 8ff97b2 | 2012-10-28 18:19:38 +0800 | [diff] [blame] | 242 | CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8scm_cpu2cpu_limit_list[2] = |
| 243 | { |
| 244 | { |
| 245 | /* On the reference platform, these settings apply to all coherent links */ |
| 246 | HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, |
| 247 | |
| 248 | /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */ |
| 249 | HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY, |
| 250 | }, |
| 251 | |
| 252 | /* The 2nd element in the array merely terminates the list */ |
| 253 | { |
| 254 | HT_LIST_TERMINAL, |
| 255 | } |
| 256 | }; |
| 257 | |
| 258 | CONST IO_PCB_LIMITS ROMDATA h8scm_io_limit_list[2] = |
| 259 | { |
| 260 | { |
| 261 | /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ |
| 262 | HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, |
| 263 | |
| 264 | /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */ |
| 265 | HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY, |
| 266 | }, |
| 267 | |
| 268 | /* The 2nd element in the array merely terminates the list */ |
| 269 | { |
| 270 | HT_LIST_TERMINAL |
| 271 | } |
| 272 | }; |
Kyösti Mälkki | 225da64 | 2015-02-04 13:46:12 +0200 | [diff] [blame] | 273 | #endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */ |
Siyuan Wang | 8ff97b2 | 2012-10-28 18:19:38 +0800 | [diff] [blame] | 274 | |
| 275 | /** |
| 276 | * HyperTransport links will typically require an equalization at high frequencies. |
| 277 | * This is called deemphasis. |
| 278 | * |
| 279 | * Deemphasis is specified as levels, for example, -3 db. |
| 280 | * There are two levels for each link, its receiver deemphasis level and its DCV level, |
| 281 | * which is based on the far side transmitter's deemphasis. |
| 282 | * For each link, different levels may be required at each link frequency. |
| 283 | * |
| 284 | * Coherent connections between processors should have an entry for the port on each processor. |
| 285 | * There should be one entry for the host root port of each non-coherent chain. |
| 286 | * |
| 287 | * AGESA initialization code does not set deemphasis on IO Devices. |
| 288 | * A default is provided for internal links of MCM processors, and |
| 289 | * those links will generally not need deemphasis structures. |
| 290 | */ |
| 291 | CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8scm_deemphasis_list[] = |
| 292 | { |
| 293 | /* Socket, Link, LowFreq, HighFreq, Receiver Deemphasis, Dcv Deemphasis */ |
| 294 | |
| 295 | /* Non-coherent link deemphasis. */ |
| 296 | {0, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, |
| 297 | {0, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, |
| 298 | {0, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, |
| 299 | {0, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, |
| 300 | {0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, |
| 301 | {0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, |
| 302 | |
| 303 | /* Coherent link deemphasis. */ |
| 304 | {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, |
| 305 | {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3}, |
| 306 | {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus6}, |
| 307 | {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus6}, |
| 308 | {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus8}, |
| 309 | {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2600M, HT_FREQUENCY_MAX, DeemphasisLevelMinus11pre8, DcvLevelMinus11}, |
| 310 | |
| 311 | /* End of the list */ |
| 312 | { |
| 313 | HT_LIST_TERMINAL |
| 314 | } |
| 315 | }; |
| 316 | |
| 317 | CONST AP_MTRR_SETTINGS ROMDATA h8scm_ap_mtrr_list[] = |
| 318 | { |
| 319 | {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E}, |
| 320 | {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E}, |
| 321 | {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000}, |
| 322 | {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000}, |
| 323 | {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000}, |
| 324 | {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000}, |
| 325 | {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000}, |
| 326 | {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818}, |
| 327 | {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818}, |
| 328 | {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818}, |
| 329 | {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818}, |
| 330 | {CPU_LIST_TERMINAL} |
| 331 | }; |
| 332 | |
| 333 | #define BLDCFG_BUID_SWAP_LIST &h8scm_manual_swaplist |
| 334 | #define BLDCFG_HTFABRIC_LIMITS_LIST &h8scm_cpu2cpu_limit_list |
| 335 | #define BLDCFG_HTCHAIN_LIMITS_LIST &h8scm_io_limit_list |
| 336 | #define BLDCFG_PLATFORM_DEEMPHASIS_LIST &h8scm_deemphasis_list |
| 337 | #define BLDCFG_AP_MTRR_SETTINGS_LIST &h8scm_ap_mtrr_list |
| 338 | |
| 339 | /* Process the options... |
| 340 | * This file include MUST occur AFTER the user option selection settings |
| 341 | */ |
| 342 | #define AGESA_ENTRY_INIT_RESET TRUE//FALSE |
| 343 | #define AGESA_ENTRY_INIT_RECOVERY FALSE |
| 344 | #define AGESA_ENTRY_INIT_EARLY TRUE |
| 345 | #define AGESA_ENTRY_INIT_POST TRUE |
| 346 | #define AGESA_ENTRY_INIT_ENV TRUE |
| 347 | #define AGESA_ENTRY_INIT_MID TRUE |
| 348 | #define AGESA_ENTRY_INIT_LATE TRUE |
| 349 | #define AGESA_ENTRY_INIT_S3SAVE TRUE |
| 350 | #define AGESA_ENTRY_INIT_RESUME TRUE |
| 351 | #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE |
| 352 | #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE |
| 353 | |
| 354 | #include "SanMarinoInstall.h" |
| 355 | |
| 356 | /*---------------------------------------------------------------------------------------- |
| 357 | * CUSTOMER OVERIDES MEMORY TABLE |
| 358 | *---------------------------------------------------------------------------------------- |
| 359 | */ |
| 360 | |
| 361 | //reference BKDG Table87: works |
| 362 | #define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM. |
| 363 | #define SEED_A 0x54 |
| 364 | #define SEED_B 0x4D |
| 365 | #define SEED_C 0x45 |
| 366 | #define SEED_D 0x40 |
| 367 | |
| 368 | #define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM. |
| 369 | |
| 370 | /* |
| 371 | * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA |
| 372 | * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable |
| 373 | * is populated, AGESA will base its settings on the data from the table. Otherwise, it will |
| 374 | * use its default conservative settings. |
| 375 | * I am not sure whether DefaultPlatformMemoryConfiguration is necessary. |
| 376 | * If I comment out these code, H8SCM will still pass mem training. |
| 377 | */ |
| 378 | CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { |
| 379 | // |
| 380 | // The following macros are supported (use comma to separate macros): |
| 381 | // |
| 382 | // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) |
| 383 | // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. |
| 384 | // AGESA will base on this value to disable unused MemClk to save power. |
| 385 | // Example: |
| 386 | // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: |
| 387 | // Bit AM3/S1g3 pin name |
| 388 | // 0 M[B,A]_CLK_H/L[0] |
| 389 | // 1 M[B,A]_CLK_H/L[1] |
| 390 | // 2 M[B,A]_CLK_H/L[2] |
| 391 | // 3 M[B,A]_CLK_H/L[3] |
| 392 | // 4 M[B,A]_CLK_H/L[4] |
| 393 | // 5 M[B,A]_CLK_H/L[5] |
| 394 | // 6 M[B,A]_CLK_H/L[6] |
| 395 | // 7 M[B,A]_CLK_H/L[7] |
| 396 | // And platform has the following routing: |
| 397 | // CS0 M[B,A]_CLK_H/L[4] |
| 398 | // CS1 M[B,A]_CLK_H/L[2] |
| 399 | // CS2 M[B,A]_CLK_H/L[3] |
| 400 | // CS3 M[B,A]_CLK_H/L[5] |
| 401 | // Then platform can specify the following macro: |
| 402 | // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) |
| 403 | // |
| 404 | // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) |
| 405 | // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. |
| 406 | // AGESA will base on this value to tristate unused CKE to save power. |
| 407 | // |
| 408 | // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) |
| 409 | // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. |
| 410 | // AGESA will base on this value to tristate unused ODT pins to save power. |
| 411 | // |
| 412 | // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) |
| 413 | // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. |
| 414 | // AGESA will base on this value to tristate unused Chip select to save power. |
| 415 | // |
| 416 | // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) |
| 417 | // Specifies the number of DIMM slots per channel. |
| 418 | // |
| 419 | // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) |
| 420 | // Specifies the number of Chip selects per channel. |
| 421 | // |
| 422 | // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) |
| 423 | // Specifies the number of channels per socket. |
| 424 | // |
| 425 | // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) |
| 426 | // Specifies DDR bus speed of channel ChannelID on socket SocketID. |
| 427 | // |
| 428 | // DRAM_TECHNOLOGY(ANY_SOCKET, DDR3_TECHNOLOGY), |
| 429 | // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) |
| 430 | // |
| 431 | // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, |
| 432 | // Byte6Seed, Byte7Seed, ByteEccSeed) |
| 433 | // Specifies the write leveling seed for a channel of a socket. |
| 434 | // |
| 435 | |
| 436 | /* Specifies the write leveling seed for a channel of a socket. |
| 437 | * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, |
| 438 | * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, |
| 439 | * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, |
| 440 | * ByteEccSeed) |
| 441 | */ |
| 442 | WRITE_LEVELING_SEED( |
| 443 | ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, |
| 444 | F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, |
| 445 | F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, |
| 446 | F15_WL_SEED), |
| 447 | |
| 448 | /* HW_RXEN_SEED(SocketID, ChannelID, DimmID, |
| 449 | * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, |
| 450 | * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed) |
| 451 | */ |
| 452 | HW_RXEN_SEED( |
| 453 | ANY_SOCKET, CHANNEL_A, ALL_DIMMS, |
| 454 | SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, |
| 455 | SEED_A), |
| 456 | HW_RXEN_SEED( |
| 457 | ANY_SOCKET, CHANNEL_B, ALL_DIMMS, |
| 458 | SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, |
| 459 | SEED_B), |
| 460 | HW_RXEN_SEED( |
| 461 | ANY_SOCKET, CHANNEL_C, ALL_DIMMS, |
| 462 | SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, |
| 463 | SEED_C), |
| 464 | HW_RXEN_SEED( |
| 465 | ANY_SOCKET, CHANNEL_D, ALL_DIMMS, |
| 466 | SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, |
| 467 | SEED_D), |
| 468 | |
| 469 | NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3 |
| 470 | PSO_END |
| 471 | }; |
| 472 | |
| 473 | /* |
| 474 | * These tables are optional and may be used to adjust memory timing settings |
| 475 | */ |