Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include "NbPlatform.h" |
| 17 | #include "rd890_cfg.h" |
| 18 | #include "northbridge/amd/cimx/rd890/chip.h" |
| 19 | #include "nbInitializer.h" |
| 20 | #include <string.h> |
| 21 | #include <arch/ioapic.h> |
| 22 | |
| 23 | #ifndef __PRE_RAM__ |
| 24 | #include <device/device.h> |
| 25 | extern void set_pcie_reset(void *config); |
| 26 | extern void set_pcie_dereset(void *config); |
| 27 | |
| 28 | /** |
| 29 | * Platform dependent configuration at ramstage |
| 30 | */ |
| 31 | static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) |
| 32 | { |
| 33 | u16 i; |
| 34 | PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; |
| 35 | //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); |
| 36 | struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; |
| 37 | DEFAULT_PLATFORM_CONFIG(platform_config); |
| 38 | |
| 39 | /* update the platform depentent configuration by devicetree */ |
| 40 | rd890_info = nb_dev->chip_info; |
| 41 | platform_config.PortEnableMap = rd890_info->port_enable; |
| 42 | if (rd890_info->gpp1_configuration == 0) { |
| 43 | platform_config.Gpp1Config = GFX_CONFIG_AAAA; |
| 44 | } else if (rd890_info->gpp1_configuration == 1) { |
| 45 | platform_config.Gpp1Config = GFX_CONFIG_AABB; |
| 46 | } |
| 47 | if (rd890_info->gpp2_configuration == 0) { |
| 48 | platform_config.Gpp2Config = GFX_CONFIG_AAAA; |
| 49 | } else if (rd890_info->gpp2_configuration == 1) { |
| 50 | platform_config.Gpp2Config = GFX_CONFIG_AABB; |
| 51 | } |
| 52 | platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; |
| 53 | |
| 54 | if (platform_config.Gpp1Config != 0) { |
| 55 | pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; |
| 56 | } |
| 57 | if (platform_config.Gpp2Config != 0) { |
| 58 | pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; |
| 59 | } |
| 60 | if (platform_config.Gpp3aConfig != 0) { |
| 61 | pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; |
| 62 | } |
| 63 | |
| 64 | pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); |
| 65 | for (i = 0; i <= MAX_CORE_ID; i++) { |
| 66 | NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; |
| 67 | NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; |
| 68 | } |
| 69 | for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { |
| 70 | NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; |
| 71 | } |
| 72 | |
| 73 | for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { |
| 74 | if ((platform_config.PortEnableMap & (1 << i)) != 0) { |
| 75 | pPcieConfig->PortConfiguration[i].PortPresent = ON; |
| 76 | if ((platform_config.PortGen1Map & (1 << i)) != 0) { |
| 77 | pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; |
| 78 | } |
| 79 | if ((platform_config.PortHotplugMap & (1 << i)) != 0) { |
| 80 | u16 j; |
Edward O'Callaghan | 698dc74 | 2014-12-08 22:19:48 +1100 | [diff] [blame] | 81 | pPcieConfig->PortConfiguration[i].PortHotplug = ON; /* Enable Hotplug */ |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 82 | /* Set Hotplug descriptor info */ |
| 83 | for (j = 0; j < 8; j++) { |
| 84 | u32 PortDescriptor; |
| 85 | PortDescriptor = platform_config.PortHotplugDescriptors[j]; |
| 86 | if ((PortDescriptor & 0xF) == j) { |
| 87 | pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; |
| 88 | pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; |
| 89 | break; |
| 90 | } |
| 91 | } |
| 92 | } |
| 93 | } |
| 94 | } |
| 95 | } |
| 96 | #endif // __PRE_RAM__ |
| 97 | |
| 98 | /** |
| 99 | * @brief Entry point of Northbridge CIMx callout/CallBack |
| 100 | * |
| 101 | * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); |
| 102 | * |
Martin Roth | d63dbe8 | 2015-01-04 15:12:21 -0700 | [diff] [blame] | 103 | * @param[in] func Northbridge CIMx CallBackId |
| 104 | * @param[in] data Northbridge Input Data. |
| 105 | * @param[in] *config Northbridge configuration structure pointer. |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 106 | * |
| 107 | */ |
Stefan Reinauer | 273911c | 2015-07-30 16:17:10 -0700 | [diff] [blame] | 108 | static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config) |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 109 | { |
| 110 | u32 ret = 0; |
| 111 | #ifndef __PRE_RAM__ |
| 112 | device_t nb_dev = (device_t)data; |
| 113 | #endif |
| 114 | AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config; |
| 115 | |
| 116 | switch (func) { |
| 117 | case PHCB_AmdPortTrainingCompleted: |
| 118 | break; |
| 119 | |
| 120 | case PHCB_AmdPortResetDeassert: |
| 121 | #ifndef __PRE_RAM__ |
| 122 | set_pcie_dereset(config); |
| 123 | #endif |
| 124 | break; |
| 125 | |
| 126 | case PHCB_AmdPortResetAssert: |
| 127 | #ifndef __PRE_RAM__ |
| 128 | set_pcie_reset(config); |
| 129 | #endif |
| 130 | break; |
| 131 | |
| 132 | case PHCB_AmdPortResetSupported: |
| 133 | break; |
| 134 | case PHCB_AmdGeneratePciReset: |
| 135 | break; |
| 136 | case PHCB_AmdGetExclusionTable: |
| 137 | break; |
| 138 | case PHCB_AmdAllocateBuffer: |
| 139 | break; |
| 140 | case PHCB_AmdUpdateApicInterruptMapping: |
| 141 | break; |
| 142 | case PHCB_AmdFreeBuffer: |
| 143 | break; |
| 144 | case PHCB_AmdLocateBuffer: |
| 145 | break; |
| 146 | case PHCB_AmdReportEvent: |
| 147 | break; |
| 148 | case PHCB_AmdPcieAsmpInfo: |
| 149 | break; |
| 150 | |
| 151 | case CB_AmdSetNbPorConfig: |
| 152 | break; |
| 153 | case CB_AmdSetHtConfig: |
| 154 | /*TODO: different HT path and deempasis for each NB */ |
| 155 | nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES; |
| 156 | |
| 157 | break; |
| 158 | case CB_AmdSetPcieEarlyConfig: |
| 159 | #ifndef __PRE_RAM__ |
| 160 | nb_platform_config(nb_dev, nbConfigPtr); |
| 161 | #endif |
| 162 | break; |
| 163 | |
| 164 | case CB_AmdSetEarlyPostConfig: |
| 165 | break; |
| 166 | |
| 167 | case CB_AmdSetMidPostConfig: |
| 168 | nbConfigPtr->pNbConfig->IoApicBaseAddress = IO_APIC_ADDR; |
| 169 | #ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu |
| 170 | /* SBIOS must alloc 16K memory for IOMMU MMIO */ |
| 171 | UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress |
| 172 | LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C, |
| 173 | AccessWidth32, |
| 174 | &MmcfgBarAddress, |
| 175 | nbConfigPtr); |
| 176 | MmcfgBarAddress &= ~0xf; |
| 177 | if (MmcfgBarAddress != 0) { |
| 178 | nbConfigPtr->IommuBaseAddress = MmcfgBarAddress; |
| 179 | } |
| 180 | nbConfigPtr->IommuBaseAddress = 0; //disable iommu |
| 181 | #endif |
| 182 | break; |
| 183 | |
| 184 | case CB_AmdSetLatePostConfig: |
| 185 | break; |
| 186 | |
| 187 | case CB_AmdSetRecoveryConfig: |
| 188 | break; |
| 189 | } |
| 190 | |
| 191 | return ret; |
| 192 | } |
| 193 | |
| 194 | |
| 195 | /** |
| 196 | * @brief North Bridge CIMx configuration |
| 197 | * |
| 198 | * should be called before exeucte CIMx function. |
| 199 | * this function will be called in romstage and ramstage. |
| 200 | */ |
| 201 | void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig) |
| 202 | { |
| 203 | u16 i = 0; |
| 204 | PCI_ADDR PciAddress; |
| 205 | u32 val, sbNode, sbLink; |
| 206 | |
| 207 | if (!pConfig) { |
| 208 | return; |
| 209 | } |
| 210 | |
| 211 | memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK)); |
| 212 | for (i = 0; i < MAX_NB_COUNT; i++) { |
| 213 | pConfig->Northbridges[i].pNbConfig = &nbConfig[i]; |
| 214 | pConfig->Northbridges[i].pHtConfig = &htConfig[i]; |
| 215 | pConfig->Northbridges[i].pPcieConfig = &pcieConfig[i]; |
| 216 | pConfig->Northbridges[i].ConfigPtr = &pConfig; |
| 217 | } |
| 218 | |
| 219 | /* Initialize all NB structures */ |
| 220 | AmdInitializer(pConfig); |
| 221 | |
| 222 | pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ |
| 223 | //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; |
| 224 | pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; |
Kyösti Mälkki | 82860f8 | 2015-10-30 23:38:40 +0200 | [diff] [blame] | 225 | pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 226 | |
| 227 | /* |
| 228 | * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. |
| 229 | * Always 0:0:0 on single NB platform. |
| 230 | */ |
| 231 | pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); |
| 232 | |
| 233 | /* Set HT path to NB by SbNode and SbLink */ |
| 234 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); |
| 235 | LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); |
| 236 | sbNode = (val >> 8) & 0x07; |
| 237 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); |
| 238 | LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); |
| 239 | sbLink = (val >> 8) & 0x07; //assum ganged |
| 240 | pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; |
| 241 | pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; |
| 242 | //TODO: other NBs |
| 243 | |
| 244 | #ifndef __PRE_RAM__ |
| 245 | /* If temporrary MMIO enable set up CPU MMIO */ |
| 246 | for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) { |
| 247 | UINT32 MmioBase; |
| 248 | UINT32 LinkId; |
| 249 | UINT32 SubLinkId; |
| 250 | MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress; |
| 251 | if (MmioBase != 0) { |
| 252 | LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf; |
| 253 | SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0; |
| 254 | /* Set Limit */ |
| 255 | LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84), |
| 256 | AccessWidth32, |
| 257 | 0x0, |
| 258 | ((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6), |
| 259 | &(pConfig->Northbridges[i])); |
| 260 | /* Set Base */ |
| 261 | LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80), |
| 262 | AccessWidth32, |
| 263 | 0x0, |
| 264 | (MmioBase << 12) | 0x3, |
| 265 | &(pConfig->Northbridges[i])); |
| 266 | } |
| 267 | } |
| 268 | #endif |
| 269 | } |