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Marc Jones5dd4a202009-03-20 16:36:05 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Marc Jones5dd4a202009-03-20 16:36:05 +000016 */
17
18#include <console/console.h>
19#include <arch/smp/mpspec.h>
20#include <device/pci.h>
21#include <string.h>
22#include <stdint.h>
Marc Jones5dd4a202009-03-20 16:36:05 +000023#include <cpu/amd/amdk8_sysconf.h>
Uwe Hermann55dc2232010-10-25 15:32:07 +000024
Marc Jones5dd4a202009-03-20 16:36:05 +000025extern unsigned char bus_mcp55[8]; //1
26
27extern unsigned apicid_mcp55;
28
29extern unsigned char bus_pcix[3]; // under bus_mcp55_2
30
Myles Watson08e0fb82010-03-22 16:33:25 +000031static void *smp_write_config_table(void *v)
Marc Jones5dd4a202009-03-20 16:36:05 +000032{
Marc Jones5dd4a202009-03-20 16:36:05 +000033 struct mp_config_table *mc;
34 unsigned sbdn;
Patrick Georgi7411eab2010-11-22 14:14:56 +000035 int i, j, bus_isa;
Marc Jones5dd4a202009-03-20 16:36:05 +000036
37 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Marc Jones5dd4a202009-03-20 16:36:05 +000038
Patrick Georgic8feedd2012-02-16 18:43:25 +010039 mptable_init(mc, LOCAL_APIC_ADDR);
Marc Jones5dd4a202009-03-20 16:36:05 +000040
41 smp_write_processors(mc);
42
43 get_bus_conf();
44 sbdn = sysconf.sbdn;
45
Patrick Georgi7411eab2010-11-22 14:14:56 +000046 mptable_write_buses(mc, NULL, &bus_isa);
Marc Jones5dd4a202009-03-20 16:36:05 +000047
48/*I/O APICs: APIC ID Version State Address*/
49 {
50 device_t dev;
51 struct resource *res;
52 uint32_t dword;
53
54 dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
55 if (dev) {
56 res = find_resource(dev, PCI_BASE_ADDRESS_1);
57 if (res) {
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080058 smp_write_ioapic(mc, apicid_mcp55, 0x11,
59 res2mmio(res, 0, 0));
Marc Jones5dd4a202009-03-20 16:36:05 +000060 }
61
62 dword = 0x43c6c643;
63 pci_write_config32(dev, 0x7c, dword);
64
65 dword = 0x81001a00;
66 pci_write_config32(dev, 0x80, dword);
67
68 dword = 0xd00012d2;
69 pci_write_config32(dev, 0x84, dword);
70
71 }
72
73
74
75 }
Stefan Reinauer14e22772010-04-27 06:56:47 +000076
Patrick Georgic5b87c82010-05-20 15:28:19 +000077 mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
Marc Jones5dd4a202009-03-20 16:36:05 +000078
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
80
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
82
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
84
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
86
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
90
91 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
93
94 for(j=7; j>=2; j--) {
95 if(!bus_mcp55[j]) continue;
96 for(i=0;i<4;i++) {
97 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
98 }
99 }
100
101 for(i=0;i<4;i++) {
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4);
103 }
104
105
Stefan Reinauer14e22772010-04-27 06:56:47 +0000106 if(bus_pcix[0]) {
Marc Jones5dd4a202009-03-20 16:36:05 +0000107 for(i=0;i<2;i++) {
Stefan Reinauer14e22772010-04-27 06:56:47 +0000108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17
Marc Jones5dd4a202009-03-20 16:36:05 +0000109 }
110
111 for(i=0;i<4;i++) {
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4<<2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
113 }
114 }
115
116/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
Patrick Georgi6eb7a532011-10-07 21:42:52 +0200117 mptable_lintsrc(mc, bus_isa);
Marc Jones5dd4a202009-03-20 16:36:05 +0000118 /* There is no extension information... */
119
120 /* Compute the checksums */
Patrick Georgib0a9c5c2011-10-07 23:01:55 +0200121 return mptable_finalize(mc);
Marc Jones5dd4a202009-03-20 16:36:05 +0000122}
123
124unsigned long write_smp_table(unsigned long addr)
125{
126 void *v;
Patrick Georgic75c79b2011-10-07 22:41:07 +0200127 v = smp_write_floating_table(addr, 0);
Marc Jones5dd4a202009-03-20 16:36:05 +0000128 return (unsigned long)smp_write_config_table(v);
129}