Jonathan A. Kollasch | d924782 | 2015-10-30 18:15:55 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <arch/smp/mpspec.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <string.h> |
| 22 | #include <stdint.h> |
| 23 | #include <cpu/amd/amdk8_sysconf.h> |
| 24 | #include "mb_sysconf.h" |
| 25 | |
| 26 | static void *smp_write_config_table(void *v) |
| 27 | { |
| 28 | struct mp_config_table *mc; |
| 29 | struct mb_sysconf_t *m; |
| 30 | unsigned sbdn; |
| 31 | int i, j, bus_isa; |
| 32 | unsigned char apicpin[4]; |
| 33 | |
| 34 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 35 | |
| 36 | mptable_init(mc, LOCAL_APIC_ADDR); |
| 37 | |
| 38 | smp_write_processors(mc); |
| 39 | |
| 40 | get_bus_conf(); |
| 41 | sbdn = sysconf.sbdn; |
| 42 | m = sysconf.mb; |
| 43 | |
| 44 | mptable_write_buses(mc, NULL, &bus_isa); |
| 45 | |
| 46 | /*I/O APICs: APIC ID Version State Address*/ |
| 47 | { |
| 48 | device_t dev; |
| 49 | struct resource *res; |
| 50 | uint32_t dword; |
| 51 | |
| 52 | dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn+ 0x1,0)); |
| 53 | if (dev) { |
| 54 | res = find_resource(dev, PCI_BASE_ADDRESS_1); |
| 55 | if (res) |
| 56 | smp_write_ioapic(mc, m->apicid_mcp55, 0x11, |
| 57 | res2mmio(res, 0, 0)); |
| 58 | |
| 59 | /* Initialize interrupt mapping*/ |
| 60 | dword = pci_read_config32(dev, 0x74); |
| 61 | dword &= ~(1<<15); |
| 62 | dword |= 1<<2; |
| 63 | pci_write_config32(dev, 0x74, dword); |
| 64 | |
| 65 | dword = 0x43c6c643; |
| 66 | pci_write_config32(dev, 0x7c, dword); |
| 67 | |
| 68 | dword = 0x81001a00; |
| 69 | pci_write_config32(dev, 0x80, dword); |
| 70 | |
| 71 | dword = 0xd00012d2; |
| 72 | pci_write_config32(dev, 0x84, dword); |
| 73 | |
| 74 | } |
| 75 | |
| 76 | if (m->bus_mcp55b) { |
| 77 | dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x1,0)); |
| 78 | if (dev) { |
| 79 | res = find_resource(dev, PCI_BASE_ADDRESS_1); |
| 80 | if (res) |
| 81 | smp_write_ioapic(mc, m->apicid_mcp55b, 0x11, |
| 82 | res2mmio(res, 0, 0)); |
| 83 | |
| 84 | dword = 0x43c60000; |
| 85 | pci_write_config32(dev, 0x7c, dword); |
| 86 | |
| 87 | dword = 0x81000000; |
| 88 | pci_write_config32(dev, 0x80, dword); |
| 89 | |
| 90 | dword = 0xd00002d0; |
| 91 | pci_write_config32(dev, 0x84, dword); |
| 92 | |
| 93 | } |
| 94 | |
| 95 | } |
| 96 | |
| 97 | } |
| 98 | |
| 99 | mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); |
| 100 | |
| 101 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); // 10 |
| 102 | |
| 103 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 |
| 104 | |
| 105 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 |
| 106 | |
| 107 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23 |
| 108 | |
| 109 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 |
| 110 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 |
| 111 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 |
| 112 | |
| 113 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 |
| 114 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 |
| 115 | |
| 116 | //Slot PCIE |
| 117 | for (j = 2; j < 8; j++) { |
| 118 | device_t dev; |
| 119 | dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0)); |
| 120 | if (!dev || !dev->enabled) |
| 121 | continue; |
| 122 | for (i = 0; i < 4; i++) |
| 123 | apicpin[i] = 0x10 + (2+j+i+4-sbdn%4)%4; |
| 124 | smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin); |
| 125 | } |
| 126 | |
| 127 | //Slot PCI 32 |
| 128 | { |
| 129 | device_t dev; |
| 130 | dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0)); |
| 131 | if (dev && dev->enabled) { |
| 132 | for (i = 0; i < 4; i++) |
Jonathan A. Kollasch | 7c62e17 | 2015-11-03 10:06:38 -0600 | [diff] [blame] | 133 | apicpin[i] = 0x10 + i%4; |
Jonathan A. Kollasch | d924782 | 2015-10-30 18:15:55 -0500 | [diff] [blame] | 134 | smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin); |
| 135 | } |
| 136 | } |
| 137 | |
| 138 | if (m->bus_mcp55b) { |
| 139 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|0, m->apicid_mcp55b, 0x14); // 20 |
| 140 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|1, m->apicid_mcp55b, 0x17); // 23 |
| 141 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|2, m->apicid_mcp55b, 0x15); // 21 |
| 142 | |
| 143 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+8)<<2)|0, m->apicid_mcp55b, 0x16); // 22 |
| 144 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+9)<<2)|0, m->apicid_mcp55b, 0x15); // 21 |
| 145 | |
| 146 | |
| 147 | //Slot PCIE |
| 148 | for (j = 2; j < 8; j++) { |
| 149 | device_t dev; |
| 150 | dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x0a + j - 2 , 0)); |
| 151 | if (!dev || !dev->enabled) |
| 152 | continue; |
| 153 | for (i = 0; i < 4; i++) { |
| 154 | apicpin[i] = 0x10 + (2+j+i+4-m->sbdnb%4)%4; |
| 155 | } |
| 156 | smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55b, apicpin); |
| 157 | } |
| 158 | |
| 159 | } |
| 160 | |
| 161 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ |
| 162 | mptable_lintsrc(mc, bus_isa); |
| 163 | /* There is no extension information... */ |
| 164 | |
| 165 | /* Compute the checksums */ |
| 166 | return mptable_finalize(mc); |
| 167 | } |
| 168 | |
| 169 | unsigned long write_smp_table(unsigned long addr) |
| 170 | { |
| 171 | void *v; |
| 172 | v = smp_write_floating_table(addr, 0); |
| 173 | return (unsigned long)smp_write_config_table(v); |
| 174 | } |