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Jonathan A. Kollaschd9247822015-10-30 18:15:55 -05001if BOARD_SUNW_ULTRA40M2
2
3config BOARD_SPECIFIC_OPTIONS # dummy
4 def_bool y
5 select CPU_AMD_SOCKET_F
6 select DIMM_DDR2
7 select DIMM_REGISTERED
8 select NORTHBRIDGE_AMD_AMDK8
9 select SOUTHBRIDGE_NVIDIA_MCP55
10 select HT_CHAIN_DISTRIBUTE
11 select MCP55_USE_NIC
12 select MCP55_USE_AZA
Jonathan A. Kollasch7c62e172015-11-03 10:06:38 -060013 select SUPERIO_SMSC_DME1737
Jonathan A. Kollaschd9247822015-10-30 18:15:55 -050014 select PARALLEL_CPU_INIT
15 select HAVE_OPTION_TABLE
16 select HAVE_PIRQ_TABLE
17 select HAVE_MP_TABLE
18 select LIFT_BSP_APIC_ID
Jonathan A. Kollasch7c62e172015-11-03 10:06:38 -060019 select BOARD_ROMSIZE_KB_1024
Jonathan A. Kollaschd9247822015-10-30 18:15:55 -050020 select QRANK_DIMM_SUPPORT
21 select K8_ALLOCATE_IO_RANGE
22
23config MAINBOARD_DIR
24 string
25 default sunw/ultra40m2
26
27config DCACHE_RAM_BASE
28 hex
29 default 0xc8000
30
31config DCACHE_RAM_SIZE
32 hex
33 default 0x08000
34
35config APIC_ID_OFFSET
36 hex
37 default 0x10
38
39config MEM_TRAIN_SEQ
40 int
41 default 1
42
43config MCP55_NUM
44 int
45 default 2
46
47config MAINBOARD_PART_NUMBER
48 string
49 default "Ultra 40 M2"
50
51config MAX_CPUS
52 int
53 default 4
54
55config MAX_PHYSICAL_CPUS
56 int
57 default 2
58
59config HT_CHAIN_UNITID_BASE
60 hex
61 default 0x0
62
63config HT_CHAIN_END_UNITID_BASE
64 hex
65 default 0x20
66
67config IRQ_SLOT_COUNT
68 int
69 default 11
70
71config MCP55_PCI_E_X_0
72 int
Jonathan A. Kollasch7c62e172015-11-03 10:06:38 -060073 default 1
74
75config MCP55_PCI_E_X_1
76 int
77 default 1
Jonathan A. Kollaschd9247822015-10-30 18:15:55 -050078
79endif # BOARD_SUNW_ULTRA40M2