| Joseph Smith | 6a1dc86 | 2008-03-09 13:24:46 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| Joseph Smith | a0dbddf | 2009-05-02 00:59:03 +0000 | [diff] [blame] | 4 | * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> |
| Joseph Smith | 6a1dc86 | 2008-03-09 13:24:46 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| Joseph Smith | 6a1dc86 | 2008-03-09 13:24:46 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <spd.h> |
| 18 | |
| 19 | struct spd_entry { |
| 20 | unsigned int address; |
| 21 | unsigned int data; |
| 22 | }; |
| 23 | |
| 24 | /* |
| 25 | * The onboard 128MB PC133 memory does not have an SPD EEPROM so the values |
| 26 | * have to be set manually, the onboard memory is located in socket1 (0x51). |
| 27 | */ |
| 28 | const struct spd_entry spd_table [] = { |
| 29 | {SPD_MEMORY_TYPE, 0x04}, /* (Fundamental) memory type */ |
| 30 | {SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */ |
| 31 | {SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */ |
| 32 | {SPD_MODULE_DATA_WIDTH_LSB, 0x40}, /* Module data width (LSB) */ |
| 33 | {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ |
| 34 | {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ |
| 35 | {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on module */ |
| 36 | }; |