Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <arch/smp/mpspec.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <string.h> |
| 23 | #include <stdint.h> |
| 24 | #include <cpu/amd/amdfam14.h> |
| 25 | #include <SBPLATFORM.h> |
Stefan Reinauer | 13e4182 | 2015-04-27 14:02:36 -0700 | [diff] [blame] | 26 | #include <southbridge/amd/common/amd_pci_util.h> |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 27 | #include <drivers/generic/ioapic/chip.h> |
| 28 | #include <arch/ioapic.h> |
| 29 | |
| 30 | static void *smp_write_config_table(void *v) |
| 31 | { |
| 32 | struct mp_config_table *mc; |
| 33 | int bus_isa; |
| 34 | |
| 35 | /* |
| 36 | * By the time this function gets called, the IOAPIC registers |
| 37 | * have been written so they can be read to get the correct |
| 38 | * APIC ID and Version |
| 39 | */ |
| 40 | u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); |
| 41 | u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); |
| 42 | |
| 43 | /* Intialize the MP_Table */ |
| 44 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 45 | |
| 46 | mptable_init(mc, LOCAL_APIC_ADDR); |
| 47 | |
| 48 | /* |
| 49 | * Type 0: Processor Entries: |
| 50 | * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, |
| 51 | * CPU Signature (Stepping, Model, Family), |
| 52 | * Feature Flags |
| 53 | */ |
| 54 | smp_write_processors(mc); |
| 55 | |
| 56 | /* |
| 57 | * Type 1: Bus Entries: |
| 58 | * Bus ID, Bus Type |
| 59 | */ |
| 60 | mptable_write_buses(mc, NULL, &bus_isa); |
| 61 | |
| 62 | /* |
| 63 | * Type 2: I/O APICs: |
| 64 | * APIC ID, Version, APIC Flags:EN, Address |
| 65 | */ |
| 66 | smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); |
| 67 | |
| 68 | /* |
| 69 | * Type 3: I/O Interrupt Table Entries: |
| 70 | * Int Type, Int Polarity, Int Level, Source Bus ID, |
| 71 | * Source Bus IRQ, Dest APIC ID, Dest PIN# |
| 72 | */ |
| 73 | mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); |
| 74 | |
| 75 | /* PCI interrupts are level triggered, and are |
| 76 | * associated with a specific bus/device/function tuple. |
| 77 | */ |
| 78 | #define PCI_INT(bus, dev, fn, pin) \ |
| 79 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) |
| 80 | |
| 81 | /* APU Internal Graphic Device */ |
| 82 | PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); |
| 83 | PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); |
| 84 | |
| 85 | /* SMBUS / ACPI */ |
| 86 | PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); |
| 87 | |
| 88 | /* Southbridge HD Audio */ |
| 89 | PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); |
| 90 | |
| 91 | /* LPC */ |
| 92 | PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); |
| 93 | |
| 94 | /* USB */ |
| 95 | PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); |
| 96 | PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); |
| 97 | PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); |
| 98 | PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); |
| 99 | PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); |
| 100 | |
| 101 | /* IDE */ |
| 102 | PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); |
| 103 | |
| 104 | /* SATA */ |
| 105 | PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); |
| 106 | |
| 107 | /* on board NIC & Slot PCIE */ |
| 108 | PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ |
| 109 | PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ |
Kyösti Mälkki | 8c190f3 | 2014-11-14 16:20:22 +0200 | [diff] [blame] | 110 | PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ |
| 111 | PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 112 | |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 113 | /* PCIe PortA */ |
| 114 | PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ |
| 115 | /* PCIe PortB */ |
| 116 | PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ |
| 117 | /* PCIe PortC */ |
| 118 | PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ |
| 119 | /* PCIe PortD */ |
| 120 | PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ |
| 121 | |
| 122 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 123 | #define IO_LOCAL_INT(type, intr, apicid, pin) \ |
| 124 | smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); |
| 125 | |
| 126 | IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); |
| 127 | IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); |
| 128 | /* There is no extension information... */ |
| 129 | |
| 130 | /* Compute the checksums */ |
| 131 | return mptable_finalize(mc); |
| 132 | } |
| 133 | |
| 134 | unsigned long write_smp_table(unsigned long addr) |
| 135 | { |
| 136 | void *v; |
| 137 | v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ |
| 138 | return (unsigned long)smp_write_config_table(v); |
| 139 | } |