Marc Bertens | ea6772d | 2010-04-19 21:21:54 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl> |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; either version 2 of the License, or |
| 9 | ## (at your option) any later version. |
| 10 | ## |
| 11 | ## This program is distributed in the hope that it will be useful, |
| 12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | ## GNU General Public License for more details. |
| 15 | ## |
Marc Bertens | ea6772d | 2010-04-19 21:21:54 +0000 | [diff] [blame] | 16 | |
| 17 | chip northbridge/intel/i440bx # Northbridge |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 18 | device cpu_cluster 0 on # (L)APIC cluster |
Uwe Hermann | 2d1d9ceb | 2010-12-26 14:12:38 +0000 | [diff] [blame] | 19 | chip cpu/intel/socket_PGA370 # CPU socket |
| 20 | device lapic 0 on end # Local APIC of the CPU |
Marc Bertens | ea6772d | 2010-04-19 21:21:54 +0000 | [diff] [blame] | 21 | end |
| 22 | end |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 23 | device domain 0 on # PCI domain |
Marc Bertens | ea6772d | 2010-04-19 21:21:54 +0000 | [diff] [blame] | 24 | device pci 0.0 on end # Host bridge |
| 25 | device pci 1.0 on end # PCI/AGP bridge |
| 26 | chip southbridge/intel/i82371eb # Southbridge |
Sven Schnelle | baec034 | 2011-04-20 08:57:53 +0000 | [diff] [blame] | 27 | device pci f.0 on |
| 28 | chip southbridge/ti/pci1x2x |
| 29 | device pci 00.0 on |
Sven Schnelle | 5f22f303 | 2011-04-20 08:58:16 +0000 | [diff] [blame] | 30 | subsystemid 0x13b8 0x0000 |
Sven Schnelle | baec034 | 2011-04-20 08:57:53 +0000 | [diff] [blame] | 31 | end |
Sven Schnelle | baec034 | 2011-04-20 08:57:53 +0000 | [diff] [blame] | 32 | register "scr" = "0x08449060" |
| 33 | register "mrr" = "0x00007522" |
| 34 | end |
| 35 | end |
Marc Bertens | ea6772d | 2010-04-19 21:21:54 +0000 | [diff] [blame] | 36 | device pci 7.0 on # ISA bridge |
Uwe Hermann | 2d1d9ceb | 2010-12-26 14:12:38 +0000 | [diff] [blame] | 37 | chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787) |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 38 | device pnp 3f0.0 off end # Floppy (No connector) |
| 39 | device pnp 3f0.3 off end # Parallel port (No connector) |
Marc Bertens | ea6772d | 2010-04-19 21:21:54 +0000 | [diff] [blame] | 40 | device pnp 3f0.4 on # COM1 |
| 41 | io 0x60 = 0x3f8 |
| 42 | irq 0x70 = 4 |
| 43 | end |
| 44 | device pnp 3f0.5 on # COM2 / IR |
| 45 | io 0x60 = 0x2f8 |
| 46 | irq 0x70 = 3 |
| 47 | end |
Marc Bertens | 965c43b | 2011-01-06 23:03:46 +0000 | [diff] [blame] | 48 | device pnp 3f0.6 on # RTC |
| 49 | irq 0x63 = 0x72 |
| 50 | end |
| 51 | device pnp 3f0.7 off # PS/2 keyboard / mouse (No connector) |
| 52 | end |
| 53 | device pnp 3f0.8 on # AUX I/O |
| 54 | irq 0x24 = 0x84 # OSC |
| 55 | |
| 56 | irq 0xB2 = 0x0C # Soft power status 1 |
| 57 | irq 0xB3 = 0x05 # Soft power status 2 |
| 58 | irq 0xC0 = 0x03 # IRQ MUX control |
| 59 | |
| 60 | irq 0xC8 = 0x10 # GP50 = (I/O) output = Flashrom enable |
| 61 | irq 0xCA = 0x09 # GP52 = IRQ8 (output) |
| 62 | irq 0xCB = 0x01 # GP53 = nROMCS (output) |
| 63 | irq 0xCC = 0x11 # GP54 = (I/O) input |
| 64 | irq 0xF9 = 0x00 # read/write GP5x lines (0x1C) |
| 65 | |
| 66 | irq 0xD0 = 0x08 # GP60 = IRQ1 |
| 67 | irq 0xD1 = 0x08 # GP61 = IRQ3 |
| 68 | irq 0xD2 = 0x08 # GP62 = IRQ4 |
| 69 | irq 0xD3 = 0x11 # GP63 = (I/O) input = JP901 on board |
| 70 | irq 0xD4 = 0x11 # GP64 = (I/O) input |
| 71 | irq 0xD5 = 0x11 # GP65 = (I/O) input |
| 72 | irq 0xD6 = 0x08 # GP66 = IRQ8 |
| 73 | irq 0xD7 = 0x11 # GP67 = (I/O) input |
| 74 | irq 0xFA = 0x00 # read/write GP6x lines (0x88) |
| 75 | |
| 76 | irq 0xE0 = 0x00 # GP10 (I/O) = output |
| 77 | irq 0xE1 = 0x01 # GP11 (I/O) = input |
| 78 | irq 0xE2 = 0x08 # GP12 = P17 |
| 79 | irq 0xE3 = 0x00 # GP13 (I/O) = output = LED fault on front, active low |
| 80 | irq 0xE4 = 0x00 # GP14 (I/O) = output |
| 81 | irq 0xE5 = 0x00 # GP15 (I/O) = output |
| 82 | irq 0xE6 = 0x01 # GP16 (I/O) = input = JP900 on board, low on short, high on open |
| 83 | irq 0xE7 = 0x00 # GP17 (I/O) = output = LED alert on front, active low |
| 84 | irq 0xF6 = 0xFF # read/write GP1x lines (0xCA) |
| 85 | |
| 86 | irq 0xEF = 0x00 # GP_INT2 disable |
| 87 | irq 0xF0 = 0x00 # GP_INT1 disable |
| 88 | irq 0xF1 = 0x00 # WDT_UNITS |
| 89 | irq 0xF2 = 0x00 # WDT_VAL |
| 90 | irq 0xF3 = 0x00 # WDT_CFG |
| 91 | irq 0xF4 = 0x20 # WDT_CTRL (stop-cnt) |
| 92 | end |
| 93 | device pnp 3f0.a off # ACPI (No support yet) |
| 94 | # irq 0x60 = 0x0C |
| 95 | # irq 0x61 = 0x80 |
| 96 | end |
Marc Bertens | ea6772d | 2010-04-19 21:21:54 +0000 | [diff] [blame] | 97 | end |
| 98 | end |
| 99 | device pci 7.1 on end # IDE |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 100 | device pci 7.2 off end # USB (No connector) |
| 101 | device pci 7.3 off end # ACPI (No support yet) |
Marc Bertens | ea6772d | 2010-04-19 21:21:54 +0000 | [diff] [blame] | 102 | register "ide0_enable" = "1" |
| 103 | register "ide1_enable" = "1" |
| 104 | register "ide_legacy_enable" = "1" |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 105 | # Disable UDMA/33 for lower speed if your IDE device(s) don't support it. |
| 106 | register "ide0_drive0_udma33_enable" = "1" |
| 107 | register "ide0_drive1_udma33_enable" = "1" |
| 108 | register "ide1_drive0_udma33_enable" = "1" |
| 109 | register "ide1_drive1_udma33_enable" = "1" |
Marc Bertens | ea6772d | 2010-04-19 21:21:54 +0000 | [diff] [blame] | 110 | end |
Marc Bertens | ea6772d | 2010-04-19 21:21:54 +0000 | [diff] [blame] | 111 | end |
| 112 | end |