Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2006 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * |
| 7 | * Copyright (C) 2006 MSI |
| 8 | * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <arch/smp/mpspec.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <string.h> |
| 25 | #include <stdint.h> |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 26 | #include <cpu/amd/amdk8_sysconf.h> |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 27 | #include "mb_sysconf.h" |
| 28 | |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 29 | static void *smp_write_config_table(void *v) |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 30 | { |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 31 | struct mp_config_table *mc; |
Stefan Reinauer | f8b1923 | 2010-04-07 00:38:09 +0000 | [diff] [blame] | 32 | struct mb_sysconf_t *m; |
| 33 | unsigned sbdn; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 34 | |
Patrick Georgi | 5244e1b | 2010-11-21 14:41:07 +0000 | [diff] [blame] | 35 | int i, j, bus_isa; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 36 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 37 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 38 | |
Patrick Georgi | c8feedd | 2012-02-16 18:43:25 +0100 | [diff] [blame] | 39 | mptable_init(mc, LOCAL_APIC_ADDR); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 40 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 41 | smp_write_processors(mc); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 42 | |
Patrick Georgi | 5244e1b | 2010-11-21 14:41:07 +0000 | [diff] [blame] | 43 | get_bus_conf(); |
| 44 | sbdn = sysconf.sbdn; |
| 45 | m = sysconf.mb; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 46 | |
Patrick Georgi | 5244e1b | 2010-11-21 14:41:07 +0000 | [diff] [blame] | 47 | mptable_write_buses(mc, NULL, &bus_isa); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 48 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 49 | /*I/O APICs: APIC ID Version State Address*/ |
| 50 | { |
| 51 | device_t dev; |
| 52 | struct resource *res; |
| 53 | uint32_t dword; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 54 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 55 | dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); |
| 56 | if (dev) { |
| 57 | res = find_resource(dev, PCI_BASE_ADDRESS_1); |
| 58 | if (res) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 59 | smp_write_ioapic(mc, m->apicid_mcp55, 0x11, |
| 60 | res2mmio(res, 0, 0)); |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 61 | } |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 62 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 63 | dword = 0x43c6c643; |
| 64 | pci_write_config32(dev, 0x7c, dword); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 65 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 66 | dword = 0x81001a00; |
| 67 | pci_write_config32(dev, 0x80, dword); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 68 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 69 | dword = 0xd00002d2; |
| 70 | pci_write_config32(dev, 0x84, dword); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 71 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 72 | } |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 73 | |
| 74 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 75 | } |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 76 | |
Patrick Georgi | 5244e1b | 2010-11-21 14:41:07 +0000 | [diff] [blame] | 77 | mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 78 | |
| 79 | //SMBUS |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 80 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 81 | |
| 82 | //USB1.1 |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 83 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 84 | |
| 85 | //USB2.0 |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 86 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 87 | |
| 88 | //SATA1 |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 89 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 90 | |
| 91 | //SATA2 |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 92 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 93 | |
| 94 | //SATA3 |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 95 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 96 | |
| 97 | //NIC1 |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 98 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 99 | //NIC2 |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 100 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 101 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 102 | for(j=7; j>=2; j--) { |
| 103 | if(!m->bus_mcp55[j]) continue; |
| 104 | for(i=0;i<4;i++) { |
| 105 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); |
| 106 | } |
| 107 | } |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 108 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 109 | for(j=0; j<1; j++) |
| 110 | for(i=0;i<4;i++) { |
| 111 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); |
| 112 | } |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 113 | |
| 114 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 115 | mptable_lintsrc(mc, bus_isa); |
| 116 | /* There is no extension information... */ |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 117 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 118 | /* Compute the checksums */ |
| 119 | return mptable_finalize(mc); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | unsigned long write_smp_table(unsigned long addr) |
| 123 | { |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 124 | void *v; |
| 125 | v = smp_write_floating_table(addr, 0); |
| 126 | return (unsigned long)smp_write_config_table(v); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 127 | } |