Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2006 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * |
| 7 | * Copyright (C) 2006 MSI |
| 8 | * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 21 | #include <console/console.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <string.h> |
| 24 | #include <stdint.h> |
| 25 | #include <arch/pirq_routing.h> |
| 26 | |
| 27 | #include <cpu/amd/amdk8_sysconf.h> |
| 28 | #include "mb_sysconf.h" |
| 29 | |
| 30 | static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 31 | uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, |
| 32 | uint8_t slot, uint8_t rfu) |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 33 | { |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 34 | pirq_info->bus = bus; |
| 35 | pirq_info->devfn = devfn; |
| 36 | pirq_info->irq[0].link = link0; |
| 37 | pirq_info->irq[0].bitmap = bitmap0; |
| 38 | pirq_info->irq[1].link = link1; |
| 39 | pirq_info->irq[1].bitmap = bitmap1; |
| 40 | pirq_info->irq[2].link = link2; |
| 41 | pirq_info->irq[2].bitmap = bitmap2; |
| 42 | pirq_info->irq[3].link = link3; |
| 43 | pirq_info->irq[3].bitmap = bitmap3; |
| 44 | pirq_info->slot = slot; |
| 45 | pirq_info->rfu = rfu; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 46 | } |
| 47 | |
Stefan Reinauer | e9de1e2 | 2010-04-07 15:30:11 +0000 | [diff] [blame] | 48 | |
Carl-Daniel Hailfinger | a5436c6 | 2008-12-22 17:41:01 +0000 | [diff] [blame] | 49 | |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 50 | unsigned long write_pirq_routing_table(unsigned long addr) |
| 51 | { |
| 52 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 53 | struct irq_routing_table *pirq; |
| 54 | struct irq_info *pirq_info; |
| 55 | unsigned slot_num; |
| 56 | uint8_t *v; |
| 57 | struct mb_sysconf_t *m; |
| 58 | unsigned sbdn; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 59 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 60 | uint8_t sum=0; |
| 61 | int i; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 62 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 63 | get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c |
| 64 | sbdn = sysconf.sbdn; |
| 65 | m = sysconf.mb; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 66 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 67 | /* Align the table to be 16 byte aligned. */ |
| 68 | addr += 15; |
| 69 | addr &= ~15; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 70 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 71 | /* This table must be between 0xf0000 & 0x100000 */ |
| 72 | printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 73 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 74 | pirq = (void *)(addr); |
| 75 | v = (uint8_t *)(addr); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 76 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 77 | pirq->signature = PIRQ_SIGNATURE; |
| 78 | pirq->version = PIRQ_VERSION; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 79 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 80 | pirq->rtr_bus = m->bus_mcp55[0]; |
| 81 | pirq->rtr_devfn = ((sbdn+6)<<3)|0; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 82 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 83 | pirq->exclusive_irqs = 0; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 84 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 85 | pirq->rtr_vendor = 0x10de; |
| 86 | pirq->rtr_device = 0x0370; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 87 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 88 | pirq->miniport_data = 0; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 89 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 90 | memset(pirq->rfu, 0, sizeof(pirq->rfu)); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 91 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 92 | pirq_info = (void *) ( &pirq->checksum + 1); |
| 93 | slot_num = 0; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 94 | //pci bridge |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 95 | write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); |
| 96 | pirq_info++; slot_num++; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 97 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 98 | for(i=1; i< sysconf.hc_possible_num; i++) { |
| 99 | if(!(sysconf.pci1234[i] & 0x1) ) continue; |
| 100 | unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; |
| 101 | unsigned devn = sysconf.hcdn[i] & 0xff; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 102 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 103 | write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); |
| 104 | pirq_info++; slot_num++; |
| 105 | } |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 106 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 107 | pirq->size = 32 + 16 * slot_num; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 108 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 109 | for (i = 0; i < pirq->size; i++) |
| 110 | sum += v[i]; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 111 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 112 | sum = pirq->checksum - sum; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 113 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 114 | if (sum != pirq->checksum) { |
| 115 | pirq->checksum = sum; |
| 116 | } |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 117 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 118 | printk(BIOS_INFO, "done.\n"); |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 119 | |
Elyes HAOUAS | d36905c | 2014-07-23 09:23:29 +0200 | [diff] [blame] | 120 | return (unsigned long) pirq_info; |
Bingxun Shi | fb1fddb | 2007-02-09 00:26:10 +0000 | [diff] [blame] | 121 | |
| 122 | } |