bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com> |
| 5 | * |
| 6 | * Copyright (C) 2006 AMD |
| 7 | * Written by Yinghai Lu <yinghailu@gmail.com> for AMD. |
| 8 | * |
| 9 | * Copyright (C) 2006 MSI |
| 10 | * Written by bxshi <bingxunshi@gmail.com> for MSI. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by |
| 14 | * the Free Software Foundation; either version 2 of the License, or |
| 15 | * (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 21 | */ |
| 22 | |
| 23 | #include <console/console.h> |
| 24 | #include <arch/smp/mpspec.h> |
| 25 | #include <arch/io.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <string.h> |
| 28 | #include <stdint.h> |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 29 | #if CONFIG_LOGICAL_CPUS |
Stefan Reinauer | 9a16e3e | 2010-03-29 14:45:36 +0000 | [diff] [blame] | 30 | #include <cpu/amd/multicore.h> |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 31 | #endif |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 32 | #include <cpu/amd/amdk8_sysconf.h> |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 33 | #include "mb_sysconf.h" |
| 34 | |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 35 | static void *smp_write_config_table(void *v) |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 36 | { |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 37 | struct mp_config_table *mc; |
| 38 | |
Patrick Georgi | 5244e1b | 2010-11-21 14:41:07 +0000 | [diff] [blame] | 39 | int i, bus_isa; |
| 40 | struct mb_sysconf_t *m; |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 41 | |
| 42 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 43 | |
Patrick Georgi | c8feedd | 2012-02-16 18:43:25 +0100 | [diff] [blame] | 44 | mptable_init(mc, LOCAL_APIC_ADDR); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 45 | |
| 46 | smp_write_processors(mc); |
| 47 | |
Patrick Georgi | 5244e1b | 2010-11-21 14:41:07 +0000 | [diff] [blame] | 48 | get_bus_conf(); |
| 49 | m = sysconf.mb; |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 50 | |
Patrick Georgi | 5244e1b | 2010-11-21 14:41:07 +0000 | [diff] [blame] | 51 | mptable_write_buses(mc, NULL, &bus_isa); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 52 | |
| 53 | /*I/O APICs: APIC ID Version State Address*/ |
| 54 | { |
Stefan Reinauer | c51dc44 | 2010-04-07 01:44:04 +0000 | [diff] [blame] | 55 | device_t dev = 0; |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 56 | struct resource *res; |
| 57 | for(i=0; i<3; i++) { |
| 58 | dev = dev_find_device(0x1166, 0x0235, dev); |
| 59 | if (dev) { |
| 60 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 61 | if (res) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 62 | smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, |
| 63 | res2mmio(res, 0, 0)); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 64 | } |
| 65 | } |
| 66 | } |
| 67 | |
| 68 | } |
| 69 | |
Patrick Georgi | 5244e1b | 2010-11-21 14:41:07 +0000 | [diff] [blame] | 70 | mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 71 | |
| 72 | //IDE |
| 73 | outb(0x02, 0xc00); outb(0x0e, 0xc01); |
| 74 | |
| 75 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE |
| 76 | |
| 77 | //SATA |
| 78 | outb(0x07, 0xc00); outb(0x0f, 0xc01); |
| 79 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xf); |
| 80 | |
| 81 | //USB |
| 82 | outb(0x01, 0xc00); outb(0x0a, 0xc01); |
| 83 | for(i=0;i<3;i++) { |
| 84 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); // |
| 85 | } |
| 86 | |
| 87 | |
| 88 | |
| 89 | /* enable int */ |
| 90 | /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ |
| 91 | { |
| 92 | device_t dev; |
| 93 | dev = dev_find_device(0x1166, 0x0205, 0); |
| 94 | if(dev) { |
| 95 | uint32_t dword; |
| 96 | dword = pci_read_config32(dev, 0x6c); |
| 97 | dword |= (1<<4); // enable interrupts |
| 98 | pci_write_config32(dev, 0x6c, dword); |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0 |
| 103 | // AIC 8130 Galileo Technology... |
| 104 | for(i=0;i<4;i++) { |
| 105 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); // |
| 106 | } |
| 107 | |
| 108 | |
| 109 | //pci slot (on bcm5785) |
| 110 | for(i=0;i<4;i++) { |
| 111 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); // |
| 112 | } |
| 113 | |
| 114 | |
| 115 | //onboard ati |
| 116 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1); |
| 117 | |
| 118 | //PCI-X on bcm5780 |
| 119 | for(i=0;i<4;i++) { |
| 120 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); // |
| 121 | } |
| 122 | |
| 123 | //onboard Broadcom |
| 124 | for(i=0;i<2;i++) { |
| 125 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); // |
| 126 | } |
| 127 | |
| 128 | |
| 129 | // First PCI-E x8 |
| 130 | for(i=0;i<4;i++) { |
| 131 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); // |
| 132 | } |
| 133 | |
| 134 | |
| 135 | // Second PCI-E x8 |
| 136 | for(i=0;i<4;i++) { |
| 137 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0<<2)|i, m->apicid_bcm5785[1], 0xc); // |
| 138 | } |
| 139 | |
| 140 | // Third PCI-E x1 |
| 141 | for(i=0;i<4;i++) { |
| 142 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0<<2)|i, m->apicid_bcm5785[1], 0xd); // |
| 143 | } |
| 144 | |
| 145 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ |
Patrick Georgi | 6eb7a53 | 2011-10-07 21:42:52 +0200 | [diff] [blame] | 146 | mptable_lintsrc(mc, bus_isa); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 147 | /* There is no extension information... */ |
| 148 | |
| 149 | /* Compute the checksums */ |
Patrick Georgi | b0a9c5c | 2011-10-07 23:01:55 +0200 | [diff] [blame] | 150 | return mptable_finalize(mc); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 151 | } |
| 152 | |
| 153 | unsigned long write_smp_table(unsigned long addr) |
| 154 | { |
| 155 | void *v; |
Patrick Georgi | c75c79b | 2011-10-07 22:41:07 +0200 | [diff] [blame] | 156 | v = smp_write_floating_table(addr, 0); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 157 | return (unsigned long)smp_write_config_table(v); |
| 158 | } |