Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <arch/smp/mpspec.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <arch/io.h> |
Kyösti Mälkki | b426107 | 2014-07-22 10:24:20 +0300 | [diff] [blame] | 21 | #include <arch/ioapic.h> |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 22 | #include <string.h> |
| 23 | #include <stdint.h> |
| 24 | #include <cpu/amd/amdfam14.h> |
| 25 | #include <SBPLATFORM.h> |
| 26 | |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 27 | u8 intr_data[] = { |
| 28 | [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ |
| 29 | [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ |
| 30 | [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 31 | 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 32 | 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 33 | 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 34 | 0x10,0x11,0x12,0x13 |
| 35 | }; |
| 36 | |
| 37 | static void *smp_write_config_table(void *v) |
| 38 | { |
| 39 | struct mp_config_table *mc; |
| 40 | int bus_isa; |
| 41 | |
Kyösti Mälkki | b426107 | 2014-07-22 10:24:20 +0300 | [diff] [blame] | 42 | /* |
| 43 | * By the time this function gets called, the IOAPIC registers |
| 44 | * have been written so they can be read to get the correct |
| 45 | * APIC ID and Version |
| 46 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 47 | u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); |
| 48 | u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); |
Kyösti Mälkki | b426107 | 2014-07-22 10:24:20 +0300 | [diff] [blame] | 49 | |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 50 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 51 | |
| 52 | mptable_init(mc, LOCAL_APIC_ADDR); |
Patrick Georgi | f0bd871 | 2014-09-29 20:23:29 +0200 | [diff] [blame] | 53 | memcpy(mc->mpc_oem, "AMD ", 8); |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 54 | |
| 55 | smp_write_processors(mc); |
| 56 | |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 57 | mptable_write_buses(mc, NULL, &bus_isa); |
| 58 | |
| 59 | /* I/O APICs: APIC ID Version State Address */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 60 | smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 61 | |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 62 | u8 byte; |
| 63 | |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 64 | for (byte = 0x0; byte < sizeof(intr_data); byte ++) { |
| 65 | outb(byte | 0x80, 0xC00); |
| 66 | outb(intr_data[byte], 0xC01); |
| 67 | } |
| 68 | |
| 69 | /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 70 | #define IO_LOCAL_INT(type, intr, apicid, pin) \ |
| 71 | smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); |
| 72 | |
Kyösti Mälkki | b426107 | 2014-07-22 10:24:20 +0300 | [diff] [blame] | 73 | mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 74 | |
| 75 | /* PCI interrupts are level triggered, and are |
| 76 | * associated with a specific bus/device/function tuple. |
| 77 | */ |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 78 | #define PCI_INT(bus, dev, fn, pin) \ |
Kyösti Mälkki | b426107 | 2014-07-22 10:24:20 +0300 | [diff] [blame] | 79 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 80 | |
| 81 | /* APU Internal Graphic Device*/ |
| 82 | PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); |
| 83 | PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); |
| 84 | |
| 85 | //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ |
| 86 | PCI_INT(0x0, 0x14, 0x0, 0x10); |
| 87 | /* Southbridge HD Audio: */ |
| 88 | PCI_INT(0x0, 0x14, 0x2, 0x12); |
| 89 | |
| 90 | PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ |
| 91 | PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); |
| 92 | PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); |
| 93 | PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); |
| 94 | PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); |
| 95 | PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); |
| 96 | |
| 97 | /* sata */ |
| 98 | PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); |
| 99 | |
| 100 | /* on board NIC & Slot PCIE. */ |
| 101 | |
| 102 | /* PCI slots */ |
Kyösti Mälkki | cdfb462 | 2014-07-22 15:24:15 +0300 | [diff] [blame] | 103 | device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); |
| 104 | if (dev && dev->enabled) { |
| 105 | u8 bus_pci = dev->link_list->secondary; |
| 106 | /* PCI_SLOT 0. */ |
| 107 | PCI_INT(bus_pci, 0x5, 0x0, 0x14); |
| 108 | PCI_INT(bus_pci, 0x5, 0x1, 0x15); |
| 109 | PCI_INT(bus_pci, 0x5, 0x2, 0x16); |
| 110 | PCI_INT(bus_pci, 0x5, 0x3, 0x17); |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 111 | |
Kyösti Mälkki | cdfb462 | 2014-07-22 15:24:15 +0300 | [diff] [blame] | 112 | /* PCI_SLOT 1. */ |
| 113 | PCI_INT(bus_pci, 0x6, 0x0, 0x15); |
| 114 | PCI_INT(bus_pci, 0x6, 0x1, 0x16); |
| 115 | PCI_INT(bus_pci, 0x6, 0x2, 0x17); |
| 116 | PCI_INT(bus_pci, 0x6, 0x3, 0x14); |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 117 | |
Kyösti Mälkki | cdfb462 | 2014-07-22 15:24:15 +0300 | [diff] [blame] | 118 | /* PCI_SLOT 2. */ |
| 119 | PCI_INT(bus_pci, 0x7, 0x0, 0x16); |
| 120 | PCI_INT(bus_pci, 0x7, 0x1, 0x17); |
| 121 | PCI_INT(bus_pci, 0x7, 0x2, 0x14); |
| 122 | PCI_INT(bus_pci, 0x7, 0x3, 0x15); |
| 123 | } |
Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 124 | |
| 125 | /* PCIe PortA */ |
| 126 | PCI_INT(0x0, 0x15, 0x0, 0x10); |
| 127 | /* PCIe PortB */ |
| 128 | PCI_INT(0x0, 0x15, 0x1, 0x11); |
| 129 | /* PCIe PortC */ |
| 130 | PCI_INT(0x0, 0x15, 0x2, 0x12); |
| 131 | /* PCIe PortD */ |
| 132 | PCI_INT(0x0, 0x15, 0x3, 0x13); |
| 133 | |
| 134 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 135 | IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); |
| 136 | IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); |
| 137 | /* There is no extension information... */ |
| 138 | |
| 139 | /* Compute the checksums */ |
| 140 | return mptable_finalize(mc); |
| 141 | } |
| 142 | |
| 143 | unsigned long write_smp_table(unsigned long addr) |
| 144 | { |
| 145 | void *v; |
| 146 | v = smp_write_floating_table(addr, 0); |
| 147 | return (unsigned long)smp_write_config_table(v); |
| 148 | } |