| Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H |
| 17 | #define _PLATFORM_GNB_PCIE_COMPLEX_H |
| 18 | |
| 19 | #include "Porting.h" |
| 20 | #include "AGESA.h" |
| 21 | #include "amdlib.h" |
| 22 | #include <cpu/amd/agesa/s3_resume.h> |
| 23 | |
| 24 | //GNB GPP Port4 |
| 25 | #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable |
| 26 | #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 |
| 27 | #define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 |
| 28 | #define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) |
| 29 | //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) |
| 30 | #define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced |
| 31 | |
| 32 | //GNB GPP Port5 |
| Jens Rottmann | 23d13b1 | 2013-02-28 10:24:20 +0100 | [diff] [blame] | 33 | #define GNB_GPP_PORT5_PORT_PRESENT 0 //0:Disable 1:Enable |
| Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 34 | #define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 |
| 35 | #define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 |
| 36 | #define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) |
| 37 | //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) |
| 38 | #define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced |
| 39 | |
| 40 | //GNB GPP Port6 |
| Jens Rottmann | 23d13b1 | 2013-02-28 10:24:20 +0100 | [diff] [blame] | 41 | #define GNB_GPP_PORT6_PORT_PRESENT 0 //0:Disable 1:Enable |
| Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 42 | #define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 |
| 43 | #define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 |
| 44 | #define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) |
| 45 | //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) |
| 46 | #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced |
| 47 | |
| 48 | //GNB GPP Port7 |
| 49 | #define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable |
| 50 | #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 |
| 51 | #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 |
| 52 | #define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) |
| 53 | //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) |
| 54 | #define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced |
| 55 | |
| 56 | //GNB GPP Port8 |
| 57 | #define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable |
| 58 | #define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 |
| 59 | #define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 |
| 60 | #define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) |
| 61 | //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) |
| 62 | #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced |
| 63 | |
| Jens Rottmann | 73d4965 | 2013-02-28 09:56:20 +0100 | [diff] [blame] | 64 | |
| 65 | #endif //_PLATFORM_GNB_PCIE_COMPLEX_H |