blob: a33744577a8a350d9df150d7557843f88723e495 [file] [log] [blame]
Patrick Georgibe61a172010-12-18 07:48:43 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Patrick Georgibe61a172010-12-18 07:48:43 +000014 */
15
16DefinitionBlock(
17 "dsdt.aml",
18 "DSDT",
19 0x02, // DSDT revision: ACPI v2.0
20 "COREv2", // OEM id
Paul Menzeld2e0e292013-02-04 10:31:34 +010021 "COREBOOT", // OEM table id
Patrick Georgibe61a172010-12-18 07:48:43 +000022 0x20090419 // OEM revision
23)
24{
25 // Some generic macros
26 #include "acpi/platform.asl"
27
28 // global NVS and variables
Patrick Georgi91bd3062012-02-16 19:16:14 +010029 #include <southbridge/intel/sch/acpi/globalnvs.asl>
Patrick Georgibe61a172010-12-18 07:48:43 +000030
31 // General Purpose Events
32 //#include "acpi/gpe.asl"
33
34 //#include "acpi/thermal.asl"
35
36 Scope (\_SB) {
37 Device (PCI0)
38 {
Patrick Georgi91bd3062012-02-16 19:16:14 +010039 #include <northbridge/intel/sch/acpi/sch.asl>
40 #include <southbridge/intel/sch/acpi/sch.asl>
Patrick Georgibe61a172010-12-18 07:48:43 +000041 }
42 }
43
44 /* Chipset specific sleep states */
Patrick Georgi91bd3062012-02-16 19:16:14 +010045 #include <southbridge/intel/sch/acpi/sleepstates.asl>
Patrick Georgibe61a172010-12-18 07:48:43 +000046}