Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 1 | chip northbridge/intel/sch |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 2 | # IGD Displays |
| 3 | register "gfx.ndid" = "3" |
| 4 | register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 5 | |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 6 | device cpu_cluster 0 on |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 7 | chip cpu/intel/socket_441 |
| 8 | device lapic 0 on end |
| 9 | end |
| 10 | end |
| 11 | |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 12 | device domain 0 on |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 13 | device pci 00.0 on end # host bridge |
| 14 | device pci 02.0 on end # Integrated Graphics and Video Device |
| 15 | |
| 16 | chip southbridge/intel/sch |
| 17 | register "pirqa_routing" = "0xa" |
| 18 | register "pirqb_routing" = "0xb" |
| 19 | register "pirqc_routing" = "0x5" |
| 20 | register "pirqd_routing" = "0xf" |
| 21 | register "pirqe_routing" = "0x80" |
| 22 | register "pirqf_routing" = "0x80" |
| 23 | register "pirqg_routing" = "0x80" |
| 24 | register "pirqh_routing" = "0x80" |
| 25 | |
| 26 | device pci 1a.0 on end # 26 0 USB Client |
| 27 | device pci 1b.0 on end # 27 0 HD Audio Controller |
| 28 | device pci 1c.0 on end # 28 0 PCI Express Port 1 |
| 29 | device pci 1c.1 on end # 28 1 PCI Express Port 2 |
| 30 | device pci 1d.0 on end # USB Classic UHCI Controller 1 |
| 31 | device pci 1d.1 on end # USB Classic UHCI Controller 2 |
| 32 | device pci 1d.2 on end # USB Classic UHCI Controller 3 |
| 33 | device pci 1d.7 on end # USB2 EHCI Controller |
| 34 | device pci 1e.0 on end # SDIO/MMC Port 0 |
| 35 | device pci 1e.1 on end # SDIO/MMC Port 1 |
| 36 | device pci 1e.2 on end # SDIO/MMC Port 2 |
| 37 | device pci 1f.0 on end # LPC bridge |
| 38 | device pci 1f.1 on end # PATA Controller |
| 39 | end |
| 40 | end |
| 41 | end |