Lee Leahy | 5cb9dda | 2015-05-01 10:34:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2015 Intel Corp. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | 5cb9dda | 2015-05-01 10:34:54 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <cbfs.h> |
| 18 | #include <console/console.h> |
| 19 | #include <lib.h> |
| 20 | #include <soc/gpio.h> |
| 21 | #include <soc/pci_devs.h> |
| 22 | #include <soc/romstage.h> |
| 23 | #include <string.h> |
| 24 | #include <chip.h> |
| 25 | #include "onboard.h" |
| 26 | #include <boardid.h> |
| 27 | |
| 28 | /* All FSP specific code goes in this block */ |
| 29 | void mainboard_romstage_entry(struct romstage_params *rp) |
| 30 | { |
| 31 | struct pei_data *ps = rp->pei_data; |
| 32 | |
| 33 | mainboard_fill_spd_data(ps); |
| 34 | |
| 35 | /* Call back into chipset code with platform values updated. */ |
| 36 | romstage_common(rp); |
| 37 | } |
| 38 | |
| 39 | void mainboard_memory_init_params(struct romstage_params *params, |
| 40 | MEMORY_INIT_UPD *memory_params) |
| 41 | { |
| 42 | int id; |
| 43 | id = board_id(); |
| 44 | if (id == BOARD_BCRD2) { |
| 45 | memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; |
| 46 | memory_params->PcdDvfsEnable = 0; |
| 47 | } else { |
| 48 | memory_params->PcdMemoryTypeEnable = MEM_DDR3; |
| 49 | memory_params->PcdMemorySpdPtr = |
| 50 | (u32)params->pei_data->spd_data_ch0; |
| 51 | memory_params->PcdMemChannel0Config = |
| 52 | params->pei_data->spd_ch0_config; |
| 53 | memory_params->PcdMemChannel1Config = |
| 54 | params->pei_data->spd_ch1_config; |
| 55 | } |
| 56 | } |