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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / mainboard / intel / strago / gpio_bcrd2.c
blob: 4cd622b2723a66485725c0be5fe3e1bc421e851b [file] [log] [blame]
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright(C) 2013 Google Inc.
5 * Copyright (C) 2015 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]15 */
16
17#include "irqroute.h"
18#include <soc/gpio.h>
19#include <stdlib.h>
20#include "gpio.h"
21
22/* South East Community */
23static const struct soc_gpio_map gpse_gpio_map[] = {
24 Native_M1,/* MF_PLT_CLK0 */
25 GPIO_NC, /* 01 PWM1 */
26 GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */
27 GPIO_NC, /* 03 MF_PLT_CLK4 */
28 GPIO_NC, /* 04 MF_PLT_CLK3 */
29 GPIO_NC, /* PWM0 05 */
30 GPIO_NC, /* 06 MF_PLT_CLK5 */
31 GPIO_NC, /* 07 MF_PLT_CLK2 */
32 GPIO_NC, /* 15 SDMMC2_D3_CD_B */
33 Native_M1, /* 16 SDMMC1_CLK */
34 NATIVE_PU20K(1), /* 17 SDMMC1_D0 */
35 GPIO_NC, /* 18 SDMMC2_D1 */
36 GPIO_NC, /* 19 SDMMC2_CLK */
37 NATIVE_PU20K(1),/* 20 SDMMC1_D2 */
38 GPIO_NC, /* 21 SDMMC2_D2 */
39 GPIO_NC, /* 22 SDMMC2_CMD */
40 NATIVE_PU20K(1), /* 23 SDMMC1_CMD */
41 NATIVE_PU20K(1), /* 24 SDMMC1_D1 */
42 GPIO_NC, /* 25 SDMMC2_D0 */
43 NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */
44 NATIVE_PU20K(1), /* 30 SDMMC3_D1 */
45 Native_M1, /* 31 SDMMC3_CLK */
46 NATIVE_PU20K(1), /* 32 SDMMC3_D3 */
47 NATIVE_PU20K(1), /* 33 SDMMC3_D2 */
48 NATIVE_PU20K(1), /* 34 SDMMC3_CMD */
49 NATIVE_PU20K(1), /* 35 SDMMC3_D0 */
50 NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */
51 Native_M1, /* 46 LPC_CLKRUNB */
52 NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */
53 Native_M1, /* 48 LPC_FRAMEB */
54 Native_M1, /* 49 MF_LPC_CLKOUT1 */
55 NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */
56 Native_M1, /* 51 MF_LPC_CLKOUT0 */
57 NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */
58 Native_M1,/* SPI1_MISO */
59 Native_M1, /* 61 SPI1_CS0_B */
60 Native_M1, /* SPI1_CLK */
61 NATIVE_PU20K(1), /* 63 MMC1_D6 */
62 Native_M1, /* 62 SPI1_MOSI */
63 NATIVE_PU20K(1), /* 65 MMC1_D5 */
64 GPIO_NC, /* SPI1_CS1_B 66 */
65 NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */
66 NATIVE_PU20K(1), /* 68 MMC1_D7 */
67 GPIO_NC, /* 69 MMC1_RCLK */
68 Native_M1, /* 75 GPO USB_OC1_B */
69 Native_M1, /* 76 PMU_RESETBUTTON_B */
70 GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
71 /* GPIO_ALERT 77 */
72 Native_M1, /* 78 SDMMC3_PWR_EN_B */
73 GPIO_NC, /* 79 GPI ILB_SERIRQ */
74 Native_M1, /* 80 USB_OC0_B */
75 GPI(trig_edge_both, L1, P_20K_H, non_maskable,
76 en_edge_detect, NA , NA),
77 /* 81 SDMMC3_CD_B */
78 GPIO_NC, /* 82 spkr asummed gpio number */
79 Native_M1, /* 83 SUSPWRDNACK */
80 SPARE_PIN,/* 84 spare pin */
81 Native_M1, /* 85 SDMMC3_1P8_EN */
82 GPIO_END
83};
84
85
86/* South West Community */
87static const struct soc_gpio_map gpsw_gpio_map[] = {
88 GPIO_NC, /* 00 FST_SPI_D2 */
89 Native_M1, /* 01 FST_SPI_D0 */
90 Native_M1, /* 02 FST_SPI_CLK */
91 GPIO_NC, /* 03 FST_SPI_D3 */
92 GPIO_NC, /* GPO FST_SPI_CS1_B */
93 Native_M1, /* 05 FST_SPI_D1 */
94 Native_M1, /* 06 FST_SPI_CS0_B */
Jagadish Krishnamoorthy367ddc92015-06-23 19:23:25 -0700[diff] [blame]95 GPIO_NC, /* 07 FST_SPI_CS2_B */
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]96 GPIO_NC, /* 15 UART1_RTS_B */
97 Native_M2, /* 16 UART1_RXD */
98 GPIO_NC, /* 17 UART2_RXD */
99 GPIO_NC, /* 18 UART1_CTS_B */
100 GPIO_NC, /* 19 UART2_RTS_B */
101 Native_M2, /* 20 UART1_TXD */
102 GPIO_NC, /* 21 UART2_TXD */
103 GPIO_NC, /* 22 UART2_CTS_B */
104 GPIO_NC, /* 30 MF_HDA_CLK */
105 GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */
106 GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */
107 GPIO_NC, /* 33 MF_HDA_SDO */
108 GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA),
109 /* 34 MF_HDA_DOCKRSTB */
110 GPIO_NC, /* 35 MF_HDA_SYNC */
111 GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
112 GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA),
113 /* 37 MF_HDA_DOCKENB */
114 NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
115 NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */
116 NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */
117 NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */
118 GPIO_NC, /* 49 I2C_NFC_SDA */
119 NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */
120 NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */
121 GPIO_NC, /* 52 I2C_NFC_SCL */
122 NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */
123 NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */
124 NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */
125 NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */
126 GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/
127 NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */
128 NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */
129 GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */
130 GPIO_OUT_HIGH, /* 75 SATA_GP0 */
131 GPIO_NC,
132 /* 76 GPI SATA_GP1 */
133 Native_M1, /* 77 SATA_LEDN */
134 GPIO_NC, /* 80 SATA_GP3 */
135 Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
136 GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
137 Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
138 Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
139 /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
140 Native_M1, /* 90 PCIE_CLKREQ0B */
141 GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */
142 Native_M1, /* 92 GP_SSP_2_CLK */
143 NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
144 Native_M1, /* 94 GP_SSP_2_RXD */
145 GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
146 /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
147 Native_M1, /* 96 GP_SSP_2_FS */
148 NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */
149 GPIO_END
150};
151
152
153/* North Community */
154static const struct soc_gpio_map gpn_gpio_map[] = {
155 Native_M5, /* 00 GPIO_DFX0 */
156 Native_M5, /* 01 GPIO_DFX3 */
157 Native_M1, /* 02 GPIO_DFX7 */
158 Native_M5, /* 03 GPIO_DFX1 */
159 Native_M1, /* 04 GPIO_DFX5 */
160 Native_M1, /* 05 GPIO_DFX4 */
161 GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA),
162 /* 06 GPIO_DFX8 */
163 Native_M5, /* 07 GPIO_DFX2 */
164 Native_M8, /* 08 GPIO_DFX6 */
165 GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
166 UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
167 GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
168 GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
169 /* 17 GPIO_SUS3 */
170 GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
171 /* 18 GPIO_SUS7 */
172 GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
173 /* 19 GPIO_SUS1 */
174 GPIO_NC, /* 20 GPIO_SUS5 */
175 GPI(trig_edge_high, L2, P_20K_H, non_maskable,
176 en_edge_rx_data, NA , NA),
177 /* 21 SEC_GPIO_SUS11 */
178 GPIO_NC, /* 22 GPIO_SUS4 */
179 GPIO_NC,
180 /* 23 SEC_GPIO_SUS8 */
181 Native_M6, /* 24 GPIO_SUS2 */
182 GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */
183 Native_M1, /* 26 CX_PREQ_B */
184 GPIO_NC, /* 27 SEC_GPIO_SUS9 */
185 Native_M1, /* 30 TRST_B */
186 Native_M1, /* 31 TCK */
187 GPIO_SKIP, /* 32 PROCHOT_B */
188 GPIO_SKIP, /* 33 SVID0_DATA */
189 Native_M1, /* 34 TMS */
190 GPIO_NC, /* 35 CX_PRDY_B_2 */
191 GPIO_NC, /* 36 TDO_2 */
192 Native_M1, /* 37 CX_PRDY_B */
193 GPIO_SKIP, /* 38 SVID0_ALERT_B */
194 Native_M1, /* 39 TDO */
195 GPIO_SKIP, /* 40 SVID0_CLK */
196 Native_M1, /* 41 TDI */
197 Native_M2, /* 45 GP_CAMERASB05 */
198 Native_M2, /* 46 GP_CAMERASB02 */
199 Native_M2, /* 47 GP_CAMERASB08 */
200 Native_M2, /* 48 GP_CAMERASB00 */
201 Native_M2, /* 49 GP_CAMERASBO6 */
202 GPIO_NC, /* 50 GP_CAMERASB10 */
203 Native_M2, /* 51 GP_CAMERASB03 */
204 GPIO_NC, /* 52 GP_CAMERASB09 */
205 Native_M2, /* 53 GP_CAMERASB01 */
206 Native_M2, /* 54 GP_CAMERASB07 */
207 GPIO_NC, /* 55 GP_CAMERASB11 */
208 Native_M2, /* 56 GP_CAMERASB04 */
209 GPIO_NC, /* 60 PANEL0_BKLTEN */
210 Native_M1, /* 61 HV_DDI0_HPD */
211 NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */
212 Native_M1, /* 63 PANEL1_BKLTCTL */
213 NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */
214 GPIO_NC, /* 65 PANEL0_BKLTCTL */
215 GPIO_NC, /* 66 HV_DDI0_DDC_SDA */
216 NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */
217 NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */
218 Native_M1, /* 69 PANEL1_VDDEN */
219 Native_M1, /* 70 PANEL1_BKLTEN */
220 GPIO_NC, /* 71 HV_DDI0_DDC_SCL */
221 GPIO_NC, /* 72 PANEL0_VDDEN */
222 GPIO_END
223};
224
225
226/* East Community */
227static const struct soc_gpio_map gpe_gpio_map[] = {
228 Native_M1, /* 00 PMU_SLP_S3_B */
229 GPIO_NC, /* 01 PMU_BATLOW_B */
230 Native_M1, /* 02 SUS_STAT_B */
231 Native_M1, /* 03 PMU_SLP_S0IX_B */
232 Native_M1, /* 04 PMU_AC_PRESENT */
233 Native_M1, /* 05 PMU_PLTRST_B */
234 Native_M1, /* 06 PMU_SUSCLK */
235 GPIO_NC, /* 07 PMU_SLP_LAN_B */
236 Native_M1, /* 08 PMU_PWRBTN_B */
237 Native_M1, /* 09 PMU_SLP_S4_B */
238 NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */
239 GPIO_NC, /* 11 PMU_WAKE_LAN_B */
240 GPIO_NC, /* 15 MF_GPIO_3 */
241 GPIO_NC, /* 16 MF_GPIO_7 */
242 GPIO_NC, /* 17 MF_I2C1_SCL */
243 GPIO_NC, /* 18 MF_GPIO_1 */
244 GPIO_NC, /* 19 MF_GPIO_5 */
245 GPIO_NC, /* 20 MF_GPIO_9 */
246 GPIO_NC, /* 21 MF_GPIO_0 */
247 GPIO_NC, /* 22 MF_GPIO_4 */
248 GPIO_NC, /* 23 MF_GPIO_8 */
249 GPIO_NC, /* 24 MF_GPIO_2 */
250 GPIO_NC, /* 25 MF_GPIO_6 */
251 GPIO_NC, /* 26 MF_I2C1_SDA */
252 GPIO_END
253};
254
255
256static struct soc_gpio_config gpio_config = {
257 /* BSW */
258 .north = gpn_gpio_map,
259 .southeast = gpse_gpio_map,
260 .southwest = gpsw_gpio_map,
261 .east = gpe_gpio_map
262};
263
264struct soc_gpio_config *get_override_gpios_bcrd2(void)
265{
266 return &gpio_config;
267
268}