| Marc Jones | 3b0a626 | 2015-09-15 23:05:00 -0600 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2007-2008 coresystems GmbH |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
| 17 | ## Foundation, Inc. |
| 18 | ## |
| 19 | |
| 20 | # ----------------------------------------------------------------- |
| 21 | entries |
| 22 | |
| 23 | # ----------------------------------------------------------------- |
| 24 | # Status Register A |
| 25 | # ----------------------------------------------------------------- |
| 26 | # Status Register B |
| 27 | # ----------------------------------------------------------------- |
| 28 | # Status Register C |
| 29 | #96 4 r 0 status_c_rsvd |
| 30 | #100 1 r 0 uf_flag |
| 31 | #101 1 r 0 af_flag |
| 32 | #102 1 r 0 pf_flag |
| 33 | #103 1 r 0 irqf_flag |
| 34 | # ----------------------------------------------------------------- |
| 35 | # Status Register D |
| 36 | #104 7 r 0 status_d_rsvd |
| 37 | #111 1 r 0 valid_cmos_ram |
| 38 | # ----------------------------------------------------------------- |
| 39 | # Diagnostic Status Register |
| 40 | #112 8 r 0 diag_rsvd1 |
| 41 | |
| 42 | # ----------------------------------------------------------------- |
| 43 | 0 120 r 0 reserved_memory |
| 44 | #120 264 r 0 unused |
| 45 | |
| 46 | # ----------------------------------------------------------------- |
| 47 | # RTC_BOOT_BYTE (coreboot hardcoded) |
| 48 | 384 1 e 4 boot_option |
| 49 | 385 1 e 4 last_boot |
| 50 | 388 4 r 0 reboot_bits |
| 51 | #390 2 r 0 unused? |
| 52 | |
| 53 | # ----------------------------------------------------------------- |
| 54 | # coreboot config options: console |
| 55 | 392 3 e 5 baud_rate |
| 56 | 395 4 e 6 debug_level |
| 57 | #399 1 r 0 unused |
| 58 | |
| 59 | # coreboot config options: cpu |
| 60 | 400 1 e 2 hyper_threading |
| 61 | #401 7 r 0 unused |
| 62 | |
| 63 | # coreboot config options: southbridge |
| 64 | 408 1 e 1 nmi |
| 65 | 409 2 e 7 power_on_after_fail |
| 66 | #411 5 r 0 unused |
| 67 | |
| 68 | # coreboot config options: bootloader |
| 69 | #Used by ChromeOS: |
| 70 | 416 128 r 0 vbnv |
| 71 | #544 440 r 0 unused |
| 72 | |
| 73 | # SandyBridge MRC Scrambler Seed values |
| 74 | 896 32 r 0 mrc_scrambler_seed |
| 75 | 928 32 r 0 mrc_scrambler_seed_s3 |
| 76 | |
| 77 | # coreboot config options: check sums |
| 78 | 984 16 h 0 check_sum |
| 79 | #1000 24 r 0 amd_reserved |
| 80 | |
| 81 | # ----------------------------------------------------------------- |
| 82 | |
| 83 | enumerations |
| 84 | |
| 85 | #ID value text |
| 86 | 1 0 Disable |
| 87 | 1 1 Enable |
| 88 | 2 0 Enable |
| 89 | 2 1 Disable |
| 90 | 4 0 Fallback |
| 91 | 4 1 Normal |
| 92 | 5 0 115200 |
| 93 | 5 1 57600 |
| 94 | 5 2 38400 |
| 95 | 5 3 19200 |
| 96 | 5 4 9600 |
| 97 | 5 5 4800 |
| 98 | 5 6 2400 |
| 99 | 5 7 1200 |
| 100 | 6 1 Emergency |
| 101 | 6 2 Alert |
| 102 | 6 3 Critical |
| 103 | 6 4 Error |
| 104 | 6 5 Warning |
| 105 | 6 6 Notice |
| 106 | 6 7 Info |
| 107 | 6 8 Debug |
| 108 | 6 9 Spew |
| 109 | 7 0 Disable |
| 110 | 7 1 Enable |
| 111 | 7 2 Keep |
| 112 | 8 0 AHCI |
| 113 | 8 1 Compatible |
| 114 | # ----------------------------------------------------------------- |
| 115 | checksums |
| 116 | |
| 117 | checksum 392 415 984 |