Lee Leahy | 01464a6 | 2015-05-12 18:25:25 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * Copyright (C) 2015 Intel Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Lee Leahy | 01464a6 | 2015-05-12 18:25:25 -0700 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <cbfs.h> |
| 19 | #include <console/console.h> |
| 20 | #include <string.h> |
| 21 | #include <ec/google/chromeec/ec.h> |
| 22 | #include <soc/cpu.h> |
| 23 | #include <soc/gpio.h> |
| 24 | #include <soc/pei_data.h> |
| 25 | #include <soc/pei_wrapper.h> |
| 26 | #include <soc/pm.h> |
| 27 | #include <soc/romstage.h> |
| 28 | #include "spd/spd.h" |
| 29 | |
| 30 | void mainboard_romstage_entry(struct romstage_params *params) |
| 31 | { |
| 32 | post_code(0x31); |
| 33 | /* Fill out PEI DATA */ |
| 34 | mainboard_fill_pei_data(params->pei_data); |
| 35 | mainboard_fill_spd_data(params->pei_data); |
| 36 | /* Initliaze memory */ |
| 37 | romstage_common(params); |
| 38 | } |
| 39 | |
| 40 | void mainboard_memory_init_params( |
| 41 | struct romstage_params *params, |
| 42 | MEMORY_INIT_UPD *memory_params) |
| 43 | { |
| 44 | /* Get SPD data passing strucutre and initialize it.*/ |
| 45 | if (params->pei_data->spd_data[0][0][0] != 0) { |
| 46 | memory_params->MemorySpdPtr00 = |
| 47 | (UINT32)(params->pei_data->spd_data[0][0]); |
| 48 | memory_params->MemorySpdPtr10 = |
| 49 | (UINT32)(params->pei_data->spd_data[1][0]); |
| 50 | printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", |
| 51 | memory_params->MemorySpdPtr00); |
| 52 | printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n", |
| 53 | memory_params->MemorySpdPtr01); |
| 54 | printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", |
| 55 | memory_params->MemorySpdPtr10); |
| 56 | printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n", |
| 57 | memory_params->MemorySpdPtr11); |
| 58 | } |
| 59 | /* |
| 60 | * Configure the DQ/DQS settings if required. In general the settings |
| 61 | * should be set in the FSP flash image and should not need to be |
| 62 | * changed. |
| 63 | */ |
| 64 | memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], |
| 65 | sizeof(params->pei_data->dq_map[0])); |
| 66 | memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], |
| 67 | sizeof(params->pei_data->dq_map[1])); |
| 68 | memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], |
| 69 | sizeof(params->pei_data->dqs_map[0])); |
| 70 | memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], |
| 71 | sizeof(params->pei_data->dqs_map[1])); |
| 72 | memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, |
| 73 | sizeof(params->pei_data->RcompResistor)); |
| 74 | memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, |
| 75 | sizeof(params->pei_data->RcompTarget)); |
| 76 | |
| 77 | /* update spd length*/ |
| 78 | memory_params->MemorySpdDataLen = SPD_LEN; |
| 79 | memory_params->DqPinsInterleaved = FALSE; |
| 80 | } |