Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <arch/io.h> |
| 19 | #include <device/pci_def.h> |
| 20 | #include <device/pnp_def.h> |
| 21 | #include <cpu/x86/lapic.h> |
| 22 | #include <drivers/intel/fsp1_0/fsp_util.h> |
| 23 | #include <southbridge/intel/fsp_rangeley/soc.h> |
| 24 | #include <southbridge/intel/fsp_rangeley/gpio.h> |
| 25 | #include <southbridge/intel/fsp_rangeley/romstage.h> |
| 26 | #include <arch/cpu.h> |
| 27 | #include "gpio.h" |
| 28 | |
| 29 | static void interrupt_routing_config(void) |
| 30 | { |
| 31 | u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf); |
| 32 | |
| 33 | /* |
| 34 | * Initialize Interrupt Routings for each device in ilb_base_address. |
| 35 | * IR01 map to PCIe device 0x01 ... IR31 to device 0x1F. |
| 36 | * PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23. |
| 37 | * This should match devicetree and the ACPI IRQ routing/ |
| 38 | */ |
| 39 | write32(ilb_base + ILB_ACTL, 0x0000); /* ACTL bit 2:0 SCIS IRQ9 */ |
| 40 | write16(ilb_base + ILB_IR01, 0x3210); /* IR01h IR(ABCD) - PIRQ(ABCD) */ |
| 41 | write16(ilb_base + ILB_IR02, 0x3210); /* IR02h IR(ABCD) - PIRQ(ABCD) */ |
| 42 | write16(ilb_base + ILB_IR03, 0x7654); /* IR03h IR(ABCD) - PIRQ(EFGH) */ |
| 43 | write16(ilb_base + ILB_IR04, 0x7654); /* IR04h IR(ABCD) - PIRQ(EFGH) */ |
| 44 | write16(ilb_base + ILB_IR20, 0x7654); /* IR14h IR(ABCD) - PIRQ(EFGH) */ |
| 45 | write16(ilb_base + ILB_IR22, 0x0007); /* IR16h IR(A) - PIRQ(H) */ |
| 46 | write16(ilb_base + ILB_IR23, 0x0003); /* IR17h IR(A) - PIRQ(D) */ |
| 47 | write16(ilb_base + ILB_IR24, 0x0003); /* IR18h IR(A) - PIRQ(D) */ |
| 48 | write16(ilb_base + ILB_IR31, 0x0020); /* IR1Fh IR(B) - PIRQ(C) */ |
| 49 | } |
| 50 | |
| 51 | /** |
| 52 | * /brief mainboard call for setup that needs to be done before fsp init |
| 53 | * |
| 54 | */ |
| 55 | void early_mainboard_romstage_entry(void) |
| 56 | { |
| 57 | setup_soc_gpios(&gpio_map); |
| 58 | } |
| 59 | |
| 60 | /** |
| 61 | * /brief mainboard call for setup that needs to be done after fsp init |
| 62 | * |
| 63 | */ |
| 64 | void late_mainboard_romstage_entry(void) |
| 65 | { |
| 66 | interrupt_routing_config(); |
| 67 | } |
| 68 | |
| 69 | /** |
| 70 | * Get function disables - most of these will be done automatically |
| 71 | * @param mask pointer to the function-disable bitfield |
| 72 | */ |
| 73 | void get_func_disables(uint32_t *mask) |
| 74 | { |
| 75 | |
| 76 | } |
| 77 | |
| 78 | void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) |
| 79 | { |
| 80 | /* No overrides needed */ |
| 81 | return; |
| 82 | } |