Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 15 | |
| 16 | if BOARD_INTEL_MOHONPEAK |
| 17 | |
| 18 | config BOARD_SPECIFIC_OPTIONS # dummy |
| 19 | def_bool y |
| 20 | select CPU_INTEL_SOCKET_RPGA989 |
| 21 | select NORTHBRIDGE_INTEL_FSP_RANGELEY |
| 22 | select SOUTHBRIDGE_INTEL_FSP_RANGELEY |
| 23 | select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB |
| 24 | select HAVE_ACPI_TABLES |
| 25 | select HAVE_OPTION_TABLE |
| 26 | select MMCONF_SUPPORT |
| 27 | select POST_IO |
| 28 | select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT |
| 29 | |
| 30 | config MAINBOARD_DIR |
| 31 | string |
| 32 | default intel/mohonpeak |
| 33 | |
| 34 | config MAINBOARD_PART_NUMBER |
| 35 | string |
| 36 | default "Mohon Peak CRB" |
| 37 | |
| 38 | config MAX_CPUS |
| 39 | int |
| 40 | default 16 |
| 41 | |
| 42 | config CACHE_ROM_SIZE_OVERRIDE |
| 43 | hex |
| 44 | default 0x800000 |
| 45 | |
| 46 | config FSP_FILE |
| 47 | string |
| 48 | default "../intel/fsp/rangeley/FvFsp.bin" |
| 49 | |
| 50 | config CBFS_SIZE |
| 51 | hex |
| 52 | default 0x00200000 |
| 53 | |
| 54 | config ENABLE_FSP_FAST_BOOT |
| 55 | bool |
| 56 | depends on HAVE_FSP_BIN |
| 57 | default y |
| 58 | |
| 59 | config VIRTUAL_ROM_SIZE |
| 60 | hex |
| 61 | depends on ENABLE_FSP_FAST_BOOT |
| 62 | default 0x400000 |
| 63 | |
| 64 | config FSP_PACKAGE_DEFAULT |
| 65 | bool "Configure defaults for the Intel FSP package" |
| 66 | default n |
| 67 | |
| 68 | config UART_FOR_CONSOLE |
| 69 | int |
| 70 | default 1 |
| 71 | help |
| 72 | The Mohon Peak board uses COM2 (2f8) for the serial console. |
| 73 | |
Martin Roth | 9ed54f9 | 2015-12-06 12:14:42 -0700 | [diff] [blame] | 74 | config PAYLOAD_CONFIGFILE |
| 75 | string |
| 76 | default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" |
| 77 | help |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 78 | The Avoton/Rangeley chip does not allow devices to write into the 0xe000 |
| 79 | segment. This means that USB/SATA devices will not work in SeaBIOS unless |
| 80 | we put the SeaBIOS buffer area down in the 0x9000 segment. |
| 81 | |
| 82 | endif # BOARD_INTEL_MOHONPEAK |