| Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef IRQROUTE_H |
| 18 | #define IRQROUTE_H |
| 19 | |
| Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 20 | #include <soc/intel/fsp_baytrail/include/soc/irq.h> |
| 21 | #include <soc/intel/fsp_baytrail/include/soc/pci_devs.h> |
| Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 22 | |
| 23 | /* |
| 24 | *IR02h GFX INT(A) - PIRQ A |
| 25 | *IR10h EMMC INT(ABCD) - PIRQ DEFG |
| 26 | *IR11h SDIO INT(A) - PIRQ B |
| 27 | *IR12h SD INT(A) - PIRQ C |
| 28 | *IR13h SATA INT(A) - PIRQ D |
| 29 | *IR14h XHCI INT(A) - PIRQ E |
| 30 | *IR15h LP Audio INT(A) - PIRQ F |
| 31 | *IR17h MMC INT(A) - PIRQ F |
| 32 | *IR18h SIO INT(ABCD) - PIRQ BADC |
| 33 | *IR1Ah TXE INT(A) - PIRQ F |
| 34 | *IR1Bh HD Audio INT(A) - PIRQ G |
| 35 | *IR1Ch PCIe INT(ABCD) - PIRQ EFGH |
| 36 | *IR1Dh EHCI INT(A) - PIRQ D |
| 37 | *IR1Eh SIO INT(ABCD) - PIRQ BDEF |
| 38 | *IR1Fh LPC INT(ABCD) - PIRQ HGBC |
| 39 | */ |
| Martin Roth | d08057a | 2015-02-12 22:51:57 -0700 | [diff] [blame] | 40 | |
| 41 | /* PCIe bridge routing */ |
| 42 | #define BRIDGE1_DEV PCIE_DEV |
| 43 | |
| 44 | /* PCI bridge IRQs need to be updated in both tables and need to match */ |
| 45 | #define PCIE_BRIDGE_IRQ_ROUTES \ |
| 46 | PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) |
| 47 | |
| Martin Roth | cf752fe | 2015-12-02 16:20:53 -0700 | [diff] [blame] | 48 | /* Devices set as A, A, A, A evaluate as 0, and don't get set */ |
| Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 49 | #define PCI_DEV_PIRQ_ROUTES \ |
| Martin Roth | cf752fe | 2015-12-02 16:20:53 -0700 | [diff] [blame] | 50 | PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ |
| Martin Roth | d08057a | 2015-02-12 22:51:57 -0700 | [diff] [blame] | 51 | PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ |
| 52 | PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ |
| 53 | PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ |
| 54 | PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ |
| 55 | PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ |
| 56 | PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ |
| 57 | PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ |
| 58 | PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ |
| 59 | PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ |
| 60 | PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ |
| 61 | PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ |
| 62 | PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ |
| 63 | PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ |
| 64 | PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) |
| Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 65 | |
| 66 | /* |
| 67 | * Route each PIRQ[A-H] to a PIC IRQ[0-15] |
| 68 | * Reserved: 0, 1, 2, 8, 13 |
| 69 | * PS2 keyboard: 12 |
| 70 | * ACPI/SCI: 9 |
| 71 | * Floppy: 6 |
| 72 | */ |
| 73 | #define PIRQ_PIC_ROUTES \ |
| Michael Tasche | 4d166f9 | 2015-12-02 17:34:47 +0100 | [diff] [blame] | 74 | PIRQ_PIC(A, 3), \ |
| Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 75 | PIRQ_PIC(B, 5), \ |
| 76 | PIRQ_PIC(C, 7), \ |
| 77 | PIRQ_PIC(D, 10), \ |
| 78 | PIRQ_PIC(E, 11), \ |
| 79 | PIRQ_PIC(F, 12), \ |
| 80 | PIRQ_PIC(G, 14), \ |
| 81 | PIRQ_PIC(H, 15) |
| 82 | |
| 83 | #endif /* IRQROUTE_H */ |