Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
York Yang | 4a91f64 | 2014-11-25 15:54:08 -0700 | [diff] [blame] | 5 | ## Copyright (C) 2014 Intel Corporation |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 6 | ## |
| 7 | ## This program is free software; you can redistribute it and/or modify |
| 8 | ## it under the terms of the GNU General Public License as published by |
| 9 | ## the Free Software Foundation; version 2 of the License. |
| 10 | ## |
| 11 | ## This program is distributed in the hope that it will be useful, |
| 12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | ## GNU General Public License for more details. |
| 15 | ## |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 16 | |
| 17 | if BOARD_INTEL_MINNOWMAX |
| 18 | |
| 19 | config BOARD_SPECIFIC_OPTIONS # dummy |
| 20 | def_bool y |
| 21 | select SOC_INTEL_FSP_BAYTRAIL |
Martin Roth | 1df7064 | 2014-12-04 20:46:55 -0700 | [diff] [blame] | 22 | select BOARD_ROMSIZE_KB_8192 |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 23 | select HAVE_ACPI_TABLES |
| 24 | select HAVE_OPTION_TABLE |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 25 | select TSC_MONOTONIC_TIMER |
Mohan D'Costa | f9f53eb | 2014-09-25 18:17:08 +0900 | [diff] [blame] | 26 | select HAVE_ACPI_RESUME |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 27 | |
| 28 | config MAINBOARD_DIR |
| 29 | string |
| 30 | default "intel/minnowmax" |
| 31 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 32 | config MAINBOARD_PART_NUMBER |
| 33 | string |
Martin Roth | 9aadeb5 | 2014-12-14 14:12:11 -0700 | [diff] [blame] | 34 | default "Minnow Max" |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 35 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 36 | config MAX_CPUS |
| 37 | int |
| 38 | default 16 |
| 39 | |
| 40 | config CACHE_ROM_SIZE_OVERRIDE |
| 41 | hex |
| 42 | default 0x800000 |
| 43 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 44 | config FSP_FILE |
| 45 | string |
York Yang | 4a91f64 | 2014-11-25 15:54:08 -0700 | [diff] [blame] | 46 | default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 47 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 48 | config CBFS_SIZE |
| 49 | hex |
Martin Roth | 1df7064 | 2014-12-04 20:46:55 -0700 | [diff] [blame] | 50 | default 0x00300000 |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 51 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 52 | config ENABLE_FSP_FAST_BOOT |
| 53 | bool |
| 54 | depends on HAVE_FSP_BIN |
| 55 | default y |
| 56 | |
| 57 | config VIRTUAL_ROM_SIZE |
| 58 | hex |
| 59 | depends on ENABLE_FSP_FAST_BOOT |
| 60 | default 0x800000 |
| 61 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 62 | config POST_DEVICE |
| 63 | bool |
| 64 | default n |
| 65 | |
| 66 | config VGA_BIOS |
| 67 | bool |
York Yang | 4a91f64 | 2014-11-25 15:54:08 -0700 | [diff] [blame] | 68 | default y if FSP_PACKAGE_DEFAULT |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 69 | |
| 70 | endif # BOARD_INTEL_MINNOWMAX |