blob: 823a240a58d9b61871d7e9907256e0799077494f [file] [log] [blame]
Stefan Reinauer1a08f582009-10-28 16:52:48 +00001##
2## This file is part of the coreboot project.
Stefan Reinauer14e22772010-04-27 06:56:47 +00003##
Stefan Reinauer1a08f582009-10-28 16:52:48 +00004## Copyright (C) 2007-2008 coresystems GmbH
5##
6## This program is free software; you can redistribute it and/or
7## modify it under the terms of the GNU General Public License as
Uwe Hermann2d2f0c12009-10-28 17:36:11 +00008## published by the Free Software Foundation; version 2 of the License.
Stefan Reinauer1a08f582009-10-28 16:52:48 +00009##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Stefan Reinauer1a08f582009-10-28 16:52:48 +000015
16chip northbridge/intel/i945
17
Stefan Reinauer0aa37c42013-02-12 15:20:54 -080018 device cpu_cluster 0 on
Stefan Reinauer1a08f582009-10-28 16:52:48 +000019 chip cpu/intel/socket_441
Patrick Georgi8d313682010-05-05 13:12:42 +000020 device lapic 0 on end
Stefan Reinauer1a08f582009-10-28 16:52:48 +000021 end
22 end
23
Stefan Reinauer4aff4452013-02-12 14:17:15 -080024 device domain 0 on
Sven Schnelle91321022011-03-01 19:58:47 +000025 subsystemid 0x8086 0x464c inherit
Stefan Reinauer1a08f582009-10-28 16:52:48 +000026 device pci 00.0 on end # host bridge
27 device pci 01.0 off end # i945 PCIe root port
Myles Watsond27c08c2009-11-06 23:42:26 +000028 device pci 02.0 on end # vga controller
Stefan Reinauer1a08f582009-10-28 16:52:48 +000029 device pci 02.1 on end # display controller
30
31 chip southbridge/intel/i82801gx
32 register "pirqa_routing" = "0x05"
33 register "pirqb_routing" = "0x07"
34 register "pirqc_routing" = "0x05"
35 register "pirqd_routing" = "0x07"
36 register "pirqe_routing" = "0x80"
37 register "pirqf_routing" = "0x80"
38 register "pirqg_routing" = "0x80"
39 register "pirqh_routing" = "0x06"
40
41 # GPI routing
42 # 0 No effect (default)
43 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
44 # 2 SCI (if corresponding GPIO_EN bit is also set)
45 register "gpi13_routing" = "1"
46 register "gpe0_en" = "0x20000601"
47
48 register "ide_legacy_combined" = "0x1"
49 register "ide_enable_primary" = "0x1"
50 register "ide_enable_secondary" = "0x0"
51 register "sata_ahci" = "0x0"
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +020052 register "c3_latency" = "85"
53 register "p_cnt_throttling_supported" = "0"
Stefan Reinauer1a08f582009-10-28 16:52:48 +000054
55 device pci 1b.0 on end # High Definition Audio
56 device pci 1c.0 on end # PCIe
57 device pci 1c.1 on end # PCIe
58 device pci 1c.2 on end # PCIe
59 #device pci 1c.3 off end # PCIe port 4
60 #device pci 1c.4 off end # PCIe port 5
61 #device pci 1c.5 off end # PCIe port 6
62 device pci 1d.0 on end # USB UHCI
63 device pci 1d.1 on end # USB UHCI
64 device pci 1d.2 on end # USB UHCI
65 device pci 1d.3 on end # USB UHCI
66 device pci 1d.7 on end # USB2 EHCI
67 device pci 1e.0 on end # PCI bridge
Stefan Reinauer14e22772010-04-27 06:56:47 +000068 #device pci 1e.2 off end # AC'97 Audio
Stefan Reinauer1a08f582009-10-28 16:52:48 +000069 #device pci 1e.3 off end # AC'97 Modem
70 device pci 1f.0 on # LPC bridge
71 chip superio/smsc/lpc47m15x
72 device pnp 2e.0 off # Floppy
73 end
74 device pnp 2e.3 off # Parport
75 end
76 device pnp 2e.4 on
77 io 0x60 = 0x3f8
78 irq 0x70 = 4
79 end
80 device pnp 2e.5 on
81 io 0x60 = 0x2f8
82 irq 0x70 = 3
83 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
84 end
85 device pnp 2e.7 on # Keyboard+Mouse
86 io 0x60 = 0x60
87 io 0x62 = 0x64
88 irq 0x70 = 1
89 irq 0x72 = 12
90 irq 0xf0 = 0x82 # HW accel A20.
91 end
92 device pnp 2e.8 on # GAME
93 # all default
94 end
95 device pnp 2e.a on # PME
96 end
97 device pnp 2e.b on # MPU
98 end
99 end
100 end
101 #device pci 1f.1 off end # IDE
102 device pci 1f.2 on end # SATA
103 device pci 1f.3 on end # SMBus
104 #device pci 1f.4 off end # Realtek ID Codec
105 end
106 end
107end