blob: c1f72f9ac33d2744afaaf5ae5aa78a1adaf68546 [file] [log] [blame]
Damien Zammit74d165b2015-05-04 10:41:21 +10001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17DefinitionBlock(
18 "dsdt.aml",
19 "DSDT",
20 0x02, // DSDT revision: ACPI v2.0
21 "COREv4", // OEM id
22 "COREBOOT", // OEM table id
23 0x20090419 // OEM revision
24)
25{
26 #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
27
28 Scope (\_SB) {
29 Device (PCI0)
30 {
31 #include <northbridge/intel/pineview/acpi/pineview.asl>
32 #include <southbridge/intel/i82801gx/acpi/ich7.asl>
33 }
34 }
35
36 /* Chipset specific sleep states */
37 #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
38}