Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 15 | |
| 16 | if BOARD_INTEL_BAKERSPORT_FSP |
| 17 | |
| 18 | config BOARD_SPECIFIC_OPTIONS # dummy |
| 19 | def_bool y |
| 20 | select SOC_INTEL_FSP_BAYTRAIL |
| 21 | select BOARD_ROMSIZE_KB_2048 |
| 22 | select HAVE_ACPI_TABLES |
| 23 | select HAVE_OPTION_TABLE |
Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 24 | select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT |
| 25 | select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT |
Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 26 | select TSC_MONOTONIC_TIMER |
| 27 | |
| 28 | config MAINBOARD_DIR |
| 29 | string |
| 30 | default "intel/bayleybay_fsp" |
| 31 | |
Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 32 | config MAINBOARD_PART_NUMBER |
| 33 | string |
Vladimir Serbinenko | 7411657 | 2014-10-24 19:30:06 +0200 | [diff] [blame] | 34 | default "Bakersport CRB (FSP)" |
Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 35 | |
Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 36 | config MAX_CPUS |
| 37 | int |
| 38 | default 16 |
| 39 | |
| 40 | config CACHE_ROM_SIZE_OVERRIDE |
| 41 | hex |
| 42 | default 0x800000 |
| 43 | |
| 44 | config FSP_FILE |
| 45 | string |
| 46 | default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP |
| 47 | |
Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 48 | config CBFS_SIZE |
| 49 | hex |
| 50 | default 0x00200000 |
| 51 | |
Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 52 | config ENABLE_FSP_FAST_BOOT |
| 53 | bool |
| 54 | depends on HAVE_FSP_BIN |
| 55 | default y |
| 56 | |
| 57 | config VIRTUAL_ROM_SIZE |
| 58 | hex |
| 59 | depends on ENABLE_FSP_FAST_BOOT |
| 60 | default 0x800000 |
| 61 | |
| 62 | config FSP_PACKAGE_DEFAULT |
| 63 | bool "Configure defaults for the Intel FSP package" |
| 64 | default n |
| 65 | |
| 66 | config VGA_BIOS |
| 67 | bool |
| 68 | default y if FSP_PACKAGE_DEFAULT |
| 69 | |
| 70 | endif # BOARD_INTEL_BAKERSPORT_FSP |