Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | // __PRE_RAM__ means: use "unsigned" for device, not a struct. |
| 17 | |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 18 | #include <stdint.h> |
| 19 | #include <string.h> |
| 20 | #include <arch/io.h> |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 21 | #include <device/pci_def.h> |
| 22 | #include <device/pnp_def.h> |
| 23 | #include <cpu/x86/lapic.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 24 | #include <lib.h> |
Kyösti Mälkki | 12d681b | 2014-06-14 18:51:34 +0300 | [diff] [blame] | 25 | #include <arch/acpi.h> |
Kyösti Mälkki | a7c9611 | 2013-10-13 20:41:57 +0300 | [diff] [blame] | 26 | #include <cbmem.h> |
Edward O'Callaghan | 9e308b9 | 2014-04-27 23:28:31 +1000 | [diff] [blame] | 27 | #include <superio/winbond/common/winbond.h> |
Edward O'Callaghan | 9c65978 | 2014-06-01 16:31:48 +1000 | [diff] [blame] | 28 | #include <superio/winbond/w83627ehg/w83627ehg.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 29 | #include <pc80/mc146818rtc.h> |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 30 | #include <console/console.h> |
| 31 | #include <cpu/x86/bist.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 32 | #include <halt.h> |
Edward O'Callaghan | 2c9e370 | 2014-05-21 06:51:15 +1000 | [diff] [blame] | 33 | #include <northbridge/intel/i945/i945.h> |
| 34 | #include <northbridge/intel/i945/raminit.h> |
| 35 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 36 | |
Uwe Hermann | 57b2ff8 | 2010-11-21 17:29:59 +0000 | [diff] [blame] | 37 | #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) |
Uwe Hermann | 3a4ed15 | 2010-12-05 22:36:14 +0000 | [diff] [blame] | 38 | #define DUMMY_DEV PNP_DEV(0x4e, 0) |
Uwe Hermann | 57b2ff8 | 2010-11-21 17:29:59 +0000 | [diff] [blame] | 39 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 40 | void setup_ich7_gpios(void) |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 41 | { |
| 42 | printk(BIOS_DEBUG, " GPIOS..."); |
| 43 | /* General Registers */ |
| 44 | outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ |
| 45 | outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ |
| 46 | outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 47 | /* Output Control Registers */ |
| 48 | outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ |
| 49 | /* Input Control Registers */ |
| 50 | outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ |
| 51 | outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ |
| 52 | outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ |
| 53 | outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ |
| 54 | } |
| 55 | |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 56 | static void ich7_enable_lpc(void) |
| 57 | { |
| 58 | // Enable Serial IRQ |
| 59 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); |
| 60 | // Set COM1/COM2 decode range |
| 61 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); |
| 62 | // Enable COM1/COM2/KBD/SuperIO1+2 |
| 63 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); |
| 64 | // Enable HWM at 0x290 |
| 65 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291); |
| 66 | // io 0x300 decode |
| 67 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); |
| 68 | } |
| 69 | |
| 70 | /* This box has one superio |
| 71 | * Also set up the GPIOs from the beginning. This is the "no schematic |
| 72 | * but safe anyways" method. |
| 73 | */ |
| 74 | static void early_superio_config_w83627ehg(void) |
| 75 | { |
| 76 | device_t dev; |
| 77 | |
Uwe Hermann | 3a4ed15 | 2010-12-05 22:36:14 +0000 | [diff] [blame] | 78 | dev = DUMMY_DEV; |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 79 | pnp_enter_ext_func_mode(dev); |
| 80 | |
| 81 | pnp_write_config(dev, 0x24, 0xc4); // PNPCSV |
| 82 | |
| 83 | pnp_write_config(dev, 0x29, 0x01); // GPIO settings |
| 84 | pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 |
| 85 | pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings? |
| 86 | pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? |
| 87 | pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? |
| 88 | |
| 89 | dev=PNP_DEV(0x4e, W83627EHG_SP1); |
| 90 | pnp_set_logical_device(dev); |
| 91 | pnp_set_enable(dev, 0); |
| 92 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 93 | pnp_set_irq(dev, PNP_IDX_IRQ0, 4); |
| 94 | pnp_set_enable(dev, 1); |
| 95 | |
| 96 | dev=PNP_DEV(0x4e, W83627EHG_SP2); |
| 97 | pnp_set_logical_device(dev); |
| 98 | pnp_set_enable(dev, 0); |
| 99 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); |
| 100 | pnp_set_irq(dev, PNP_IDX_IRQ0, 3); |
| 101 | // pnp_write_config(dev, 0xf1, 4); // IRMODE0 |
| 102 | pnp_set_enable(dev, 1); |
| 103 | |
| 104 | dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard |
| 105 | pnp_set_logical_device(dev); |
| 106 | pnp_set_enable(dev, 0); |
| 107 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); |
| 108 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); |
| 109 | //pnp_write_config(dev, 0xf0, 0x82); |
| 110 | pnp_set_enable(dev, 1); |
| 111 | |
| 112 | dev=PNP_DEV(0x4e, W83627EHG_GPIO2); |
| 113 | pnp_set_logical_device(dev); |
| 114 | pnp_set_enable(dev, 1); // Just enable it |
| 115 | |
| 116 | dev=PNP_DEV(0x4e, W83627EHG_GPIO3); |
| 117 | pnp_set_logical_device(dev); |
| 118 | pnp_set_enable(dev, 0); |
| 119 | pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output |
| 120 | pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 |
| 121 | pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient |
| 122 | |
| 123 | dev=PNP_DEV(0x4e, W83627EHG_FDC); |
| 124 | pnp_set_logical_device(dev); |
| 125 | pnp_set_enable(dev, 0); |
| 126 | |
| 127 | dev=PNP_DEV(0x4e, W83627EHG_PP); |
| 128 | pnp_set_logical_device(dev); |
| 129 | pnp_set_enable(dev, 0); |
| 130 | |
| 131 | /* Enable HWM */ |
| 132 | dev=PNP_DEV(0x4e, W83627EHG_HWM); |
| 133 | pnp_set_logical_device(dev); |
| 134 | pnp_set_enable(dev, 0); |
| 135 | pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); |
| 136 | pnp_set_enable(dev, 1); |
| 137 | |
| 138 | pnp_exit_ext_func_mode(dev); |
| 139 | } |
| 140 | |
| 141 | static void rcba_config(void) |
| 142 | { |
| 143 | /* Set up virtual channel 0 */ |
| 144 | //RCBA32(0x0014) = 0x80000001; |
| 145 | //RCBA32(0x001c) = 0x03128010; |
| 146 | |
| 147 | /* Device 1f interrupt pin register */ |
| 148 | RCBA32(0x3100) = 0x00042210; |
| 149 | /* Device 1d interrupt pin register */ |
| 150 | RCBA32(0x310c) = 0x00214321; |
| 151 | |
| 152 | /* dev irq route register */ |
| 153 | RCBA16(0x3140) = 0x0132; |
| 154 | RCBA16(0x3142) = 0x0146; |
| 155 | RCBA16(0x3144) = 0x0237; |
| 156 | RCBA16(0x3146) = 0x3201; |
| 157 | RCBA16(0x3148) = 0x0146; |
| 158 | |
| 159 | /* Enable IOAPIC */ |
| 160 | RCBA8(0x31ff) = 0x03; |
| 161 | |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 162 | /* Enable PCIe Root Port Clock Gate */ |
| 163 | // RCBA32(0x341c) = 0x00000001; |
| 164 | } |
| 165 | |
| 166 | static void early_ich7_init(void) |
| 167 | { |
| 168 | uint8_t reg8; |
| 169 | uint32_t reg32; |
| 170 | |
| 171 | // program secondary mlt XXX byte? |
| 172 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 173 | |
| 174 | // reset rtc power status |
| 175 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 176 | reg8 &= ~(1 << 2); |
| 177 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 178 | |
| 179 | // usb transient disconnect |
| 180 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 181 | reg8 |= (3 << 0); |
| 182 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 183 | |
| 184 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 185 | reg32 |= (1 << 29) | (1 << 17); |
| 186 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 187 | |
| 188 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 189 | reg32 |= (1 << 31) | (1 << 27); |
| 190 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 191 | |
| 192 | RCBA32(0x0088) = 0x0011d000; |
| 193 | RCBA16(0x01fc) = 0x060f; |
| 194 | RCBA32(0x01f4) = 0x86000040; |
| 195 | RCBA32(0x0214) = 0x10030549; |
| 196 | RCBA32(0x0218) = 0x00020504; |
| 197 | RCBA8(0x0220) = 0xc5; |
| 198 | reg32 = RCBA32(0x3410); |
| 199 | reg32 |= (1 << 6); |
| 200 | RCBA32(0x3410) = reg32; |
| 201 | reg32 = RCBA32(0x3430); |
| 202 | reg32 &= ~(3 << 0); |
| 203 | reg32 |= (1 << 0); |
| 204 | RCBA32(0x3430) = reg32; |
| 205 | RCBA32(0x3418) |= (1 << 0); |
| 206 | RCBA16(0x0200) = 0x2008; |
| 207 | RCBA8(0x2027) = 0x0d; |
| 208 | RCBA16(0x3e08) |= (1 << 7); |
| 209 | RCBA16(0x3e48) |= (1 << 7); |
| 210 | RCBA32(0x3e0e) |= (1 << 7); |
| 211 | RCBA32(0x3e4e) |= (1 << 7); |
| 212 | |
| 213 | // next step only on ich7m b0 and later: |
| 214 | reg32 = RCBA32(0x2034); |
| 215 | reg32 &= ~(0x0f << 16); |
| 216 | reg32 |= (5 << 16); |
| 217 | RCBA32(0x2034) = reg32; |
| 218 | } |
| 219 | |
Aaron Durbin | a0a3727 | 2014-08-14 08:35:11 -0500 | [diff] [blame] | 220 | #include <cpu/intel/romstage.h> |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 221 | void main(unsigned long bist) |
| 222 | { |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 223 | int s3resume = 0; |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 224 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 225 | if (bist == 0) |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 226 | enable_lapic(); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 227 | |
| 228 | ich7_enable_lpc(); |
| 229 | early_superio_config_w83627ehg(); |
| 230 | |
| 231 | /* Set up the console */ |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 232 | console_init(); |
| 233 | |
| 234 | /* Halt if there was a built in self test failure */ |
| 235 | report_bist_failure(bist); |
| 236 | |
| 237 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 238 | printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); |
| 239 | outb(0x6, 0xcf9); |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 240 | halt(); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 241 | } |
| 242 | |
| 243 | /* Perform some early chipset initialization required |
| 244 | * before RAM initialization can work |
| 245 | */ |
| 246 | i945_early_initialization(); |
| 247 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 248 | s3resume = southbridge_detect_s3_resume(); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 249 | |
| 250 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 251 | enable_smbus(); |
| 252 | |
| 253 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 254 | dump_spd_registers(); |
| 255 | #endif |
| 256 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 257 | sdram_initialize(s3resume ? 2 : 0, NULL); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 258 | |
| 259 | /* Perform some initialization that must run before stage2 */ |
| 260 | early_ich7_init(); |
| 261 | |
| 262 | /* This should probably go away. Until now it is required |
| 263 | * and mainboard specific |
| 264 | */ |
| 265 | rcba_config(); |
| 266 | |
| 267 | /* Chipset Errata! */ |
| 268 | fixup_i945_errata(); |
| 269 | |
| 270 | /* Initialize the internal PCIe links before we go into stage2 */ |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 271 | i945_late_initialization(s3resume); |
Bernhard M. Wiedemann | 6e554de | 2010-05-30 12:56:17 +0000 | [diff] [blame] | 272 | } |