Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
Kyösti Mälkki | 34ad72c | 2014-10-21 13:43:46 +0300 | [diff] [blame] | 16 | #include "Porting.h" |
| 17 | #include "AGESA.h" |
| 18 | #include "amdlib.h" |
Alexandru Gagniuc | 1d87dac | 2014-03-28 14:48:13 -0500 | [diff] [blame] | 19 | |
Kyösti Mälkki | 34ad72c | 2014-10-21 13:43:46 +0300 | [diff] [blame] | 20 | #include <northbridge/amd/agesa/agesawrapper.h> |
Alexandru Gagniuc | 1d87dac | 2014-03-28 14:48:13 -0500 | [diff] [blame] | 21 | #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 22 | |
| 23 | #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE |
| 24 | |
| 25 | /* |
| 26 | * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) |
| 27 | * |
| 28 | * Lane Id |
| 29 | * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 |
| 30 | * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 |
| 31 | * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 |
| 32 | * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 |
| 33 | * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 |
| 34 | * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 |
| 35 | * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 |
| 36 | * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 |
| 37 | * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI |
| 38 | * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI |
| 39 | * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI |
| 40 | * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI |
| 41 | * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI |
| 42 | * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI |
| 43 | * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI |
| 44 | * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI |
| 45 | * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI |
| 46 | * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI |
| 47 | * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI |
| 48 | * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI |
| 49 | * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI |
| 50 | * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI |
| 51 | * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI |
| 52 | * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI |
| 53 | * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) |
| 54 | * 25 DP0_TX[P,N]1 |
| 55 | * 26 DP0_TX[P,N]2 |
| 56 | * 27 DP0_TX[P,N]3 |
| 57 | * 28 DP1_TX[P,N]0 |
| 58 | * 29 DP1_TX[P,N]1 |
| 59 | * 30 DP1_TX[P,N]2 |
| 60 | * 31 DP1_TX[P,N]3 |
| 61 | * 32 DP2_TX[P,N]0 |
| 62 | * 33 DP2_TX[P,N]1 |
| 63 | * 34 DP2_TX[P,N]2 |
| 64 | * 35 DP2_TX[P,N]3 |
| 65 | * 36 DP2_TX[P,N]4 |
| 66 | * 37 DP2_TX[P,N]5 |
| 67 | * 38 DP2_TX[P,N]6 |
| 68 | */ |
| 69 | |
| 70 | static const PCIe_PORT_DESCRIPTOR PortList [] = { |
| 71 | /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */ |
| 72 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 73 | 0, |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 74 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), |
| 75 | PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) |
| 76 | }, |
| 77 | /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ |
| 78 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 79 | 0, |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 80 | PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), |
| 81 | PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) |
| 82 | }, |
| 83 | |
| 84 | /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ |
| 85 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 86 | 0, |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 87 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), |
| 88 | PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) |
| 89 | }, |
| 90 | |
| 91 | /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ |
| 92 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 93 | 0, |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 94 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), |
| 95 | PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) |
| 96 | }, |
| 97 | |
| 98 | /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ |
| 99 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 100 | 0, |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 101 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), |
| 102 | PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) |
| 103 | }, |
| 104 | |
| 105 | /* PCIe port, Lanes 7, PCI Device Number 7, LAN */ |
| 106 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 107 | 0, |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 108 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), |
| 109 | PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) |
| 110 | }, |
| 111 | |
| 112 | /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ |
| 113 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 114 | DESCRIPTOR_TERMINATE_LIST, |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 115 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), |
| 116 | PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) |
| 117 | }, |
| 118 | }; |
| 119 | |
| 120 | static const PCIe_DDI_DESCRIPTOR DdiList [] = { |
| 121 | /* DP0 to HDMI0/DP */ |
| 122 | { |
| 123 | 0, |
| 124 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), |
| 125 | PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) |
| 126 | }, |
| 127 | /* DP1 to FCH */ |
| 128 | { |
| 129 | 0, |
| 130 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), |
| 131 | PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) |
| 132 | }, |
| 133 | /* DP2 to HDMI1/DP */ |
| 134 | { |
| 135 | DESCRIPTOR_TERMINATE_LIST, |
| 136 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), |
| 137 | /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) */ |
| 138 | PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) |
| 139 | }, |
| 140 | }; |
| 141 | |
| 142 | /*---------------------------------------------------------------------------------------*/ |
| 143 | /** |
| 144 | * OemCustomizeInitEarly |
| 145 | * |
| 146 | * Description: |
| 147 | * This stub function will call the host environment through the binary block |
| 148 | * interface (call-out port) to provide a user hook opportunity |
| 149 | * |
| 150 | * Parameters: |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 151 | * @param[in] *InitEarly |
| 152 | * |
| 153 | * @retval VOID |
| 154 | * |
| 155 | **/ |
| 156 | /*---------------------------------------------------------------------------------------*/ |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 157 | |
| 158 | static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 159 | { |
| 160 | AGESA_STATUS Status; |
| 161 | PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; |
| 162 | |
| 163 | ALLOCATE_HEAP_PARAMS AllocHeapParams; |
| 164 | |
| 165 | /* GNB PCIe topology Porting */ |
| 166 | |
| 167 | /* */ |
| 168 | /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ |
| 169 | /* */ |
| 170 | AllocHeapParams.RequestedBufferSize = sizeof(PCIe_COMPLEX_DESCRIPTOR); |
| 171 | |
| 172 | AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; |
| 173 | AllocHeapParams.Persist = HEAP_LOCAL_CACHE; |
| 174 | Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); |
Kyösti Mälkki | 1ef67e1 | 2014-12-16 16:45:52 +0200 | [diff] [blame] | 175 | ASSERT(Status == AGESA_SUCCESS); |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 176 | |
| 177 | PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
| 178 | |
| 179 | LibAmdMemFill (PcieComplexListPtr, |
| 180 | 0, |
| 181 | sizeof(PCIe_COMPLEX_DESCRIPTOR), |
| 182 | &InitEarly->StdHeader); |
| 183 | |
| 184 | PcieComplexListPtr->Flags = DESCRIPTOR_TERMINATE_LIST; |
| 185 | PcieComplexListPtr->SocketId = 0; |
| 186 | PcieComplexListPtr->PciePortList = PortList; |
| 187 | PcieComplexListPtr->DdiLinkList = DdiList; |
| 188 | |
| 189 | InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 190 | return AGESA_SUCCESS; |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 191 | } |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 192 | |
Kyösti Mälkki | 296696d | 2014-12-16 09:29:56 +0200 | [diff] [blame] | 193 | static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) |
| 194 | { |
| 195 | /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ |
| 196 | InitMid->GnbMidConfiguration.iGpuVgaMode = 0; |
| 197 | return AGESA_SUCCESS; |
| 198 | } |
| 199 | |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 200 | const struct OEM_HOOK OemCustomize = { |
| 201 | .InitEarly = OemInitEarly, |
Kyösti Mälkki | 296696d | 2014-12-16 09:29:56 +0200 | [diff] [blame] | 202 | .InitMid = OemInitMid, |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 203 | }; |