Oskar Enoksson | adc0a63 | 2014-02-11 22:19:35 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011,2014 Oskar Enoksson <enok@lysator.liu.se> |
| 3 | * Subject to the GNU GPL v2, or (at your option) any later version. |
| 4 | */ |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 5 | #include <stdint.h> |
| 6 | #include <string.h> |
| 7 | #include <device/pci_def.h> |
Oskar Enoksson | df073cb | 2011-10-04 22:15:51 +0200 | [diff] [blame] | 8 | #include <device/pci_ids.h> |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 9 | #include <arch/io.h> |
| 10 | #include <device/pnp_def.h> |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 11 | #include <pc80/mc146818rtc.h> |
| 12 | #include <console/console.h> |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 13 | #include <cpu/amd/model_fxx_rev.h> |
Patrick Georgi | e135ac5 | 2012-11-20 11:53:47 +0100 | [diff] [blame] | 14 | #include <delay.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 15 | #include <northbridge/amd/amdk8/amdk8.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 16 | #include "southbridge/amd/amd8111/early_smbus.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 17 | #include <northbridge/amd/amdk8/raminit.h> |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 18 | #include "northbridge/amd/amdk8/reset_test.c" |
| 19 | #include "northbridge/amd/amdk8/debug.c" |
Edward O'Callaghan | 8199809 | 2014-04-28 18:07:33 +1000 | [diff] [blame] | 20 | #include <superio/winbond/common/winbond.h> |
| 21 | #include <superio/winbond/w83627hf/w83627hf.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 22 | #include <cpu/x86/bist.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 23 | #include "southbridge/amd/amd8111/early_ctrl.c" |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 24 | |
| 25 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| 26 | |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 27 | static void memreset_setup(void) |
| 28 | { |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 29 | if (is_cpu_pre_c0()) { |
| 30 | /* Set the memreset low. */ |
| 31 | outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); |
| 32 | /* Ensure the BIOS has control of the memory lines. */ |
| 33 | outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); |
| 34 | } else { |
| 35 | /* Ensure the CPU has control of the memory lines. */ |
| 36 | outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); |
| 37 | } |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 38 | } |
| 39 | |
| 40 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 41 | { |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 42 | if (is_cpu_pre_c0()) { |
| 43 | udelay(800); |
| 44 | /* Set memreset high. */ |
| 45 | outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); |
| 46 | udelay(90); |
| 47 | } |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 48 | } |
| 49 | |
| 50 | #define SMBUS_HUB 0x18 |
| 51 | |
| 52 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 53 | { |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 54 | int ret,i; |
| 55 | unsigned device=(ctrl->channel0[0])>>8; |
| 56 | /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ |
| 57 | i=2; |
| 58 | do { |
| 59 | ret = smbus_write_byte(SMBUS_HUB, 0x01, device); |
| 60 | } while ((ret!=0) && (i-->0)); |
| 61 | smbus_write_byte(SMBUS_HUB, 0x03, 0); |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 62 | } |
| 63 | |
| 64 | static inline void change_i2c_mux(unsigned device) |
| 65 | { |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 66 | int ret, i; |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 67 | printk(BIOS_DEBUG, "change_i2c_mux i=%02x\n", device); |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 68 | i=2; |
| 69 | do { |
| 70 | ret = smbus_write_byte(SMBUS_HUB, 0x01, device); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 71 | printk(BIOS_DEBUG, "change_i2c_mux 1 ret=%08x\n", ret); |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 72 | } while ((ret!=0) && (i-->0)); |
| 73 | ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 74 | printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret); |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 78 | { |
| 79 | return smbus_read_byte(device, address); |
| 80 | } |
| 81 | |
Oskar Enoksson | df073cb | 2011-10-04 22:15:51 +0200 | [diff] [blame] | 82 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 83 | #include "northbridge/amd/amdk8/raminit.c" |
| 84 | #include "resourcemap.c" |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 85 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 86 | #include "lib/generic_sdram.c" |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 87 | #include "cpu/amd/dualcore/dualcore.c" |
Patrick Georgi | 9bd9a90 | 2010-11-20 10:31:00 +0000 | [diff] [blame] | 88 | #include <spd.h> |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 89 | #include "cpu/amd/model_fxx/init_cpus.c" |
Oskar Enoksson | aaedeca | 2014-02-11 22:51:03 +0100 | [diff] [blame] | 90 | #if CONFIG_SET_FIDVID |
| 91 | #include "cpu/amd/model_fxx/fidvid.c" |
| 92 | #endif |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 93 | |
Oskar Enoksson | df073cb | 2011-10-04 22:15:51 +0200 | [diff] [blame] | 94 | #define RC0 ((1<<1)<<8) |
| 95 | #define RC1 ((1<<2)<<8) |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 96 | |
| 97 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 98 | { |
| 99 | static const uint16_t spd_addr [] = { |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 100 | //first node |
| 101 | RC0|DIMM0, RC0|DIMM2, 0, 0, |
| 102 | RC0|DIMM1, RC0|DIMM3, 0, 0, |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 103 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 104 | //second node |
| 105 | RC1|DIMM0, RC1|DIMM2, 0, 0, |
| 106 | RC1|DIMM1, RC1|DIMM3, 0, 0, |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 107 | #endif |
| 108 | }; |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 109 | struct sys_info *sysinfo = &sysinfo_car; |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 110 | |
Oskar Enoksson | df073cb | 2011-10-04 22:15:51 +0200 | [diff] [blame] | 111 | int needs_reset = 0; |
| 112 | unsigned bsp_apicid = 0; |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 113 | |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 114 | if (bist == 0) |
| 115 | bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo); |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 116 | |
Edward O'Callaghan | 8199809 | 2014-04-28 18:07:33 +1000 | [diff] [blame] | 117 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 118 | console_init(); |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 119 | |
| 120 | /* Halt if there was a built in self test failure */ |
| 121 | report_bist_failure(bist); |
| 122 | |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 123 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Oskar Enoksson | df073cb | 2011-10-04 22:15:51 +0200 | [diff] [blame] | 124 | |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 125 | setup_dl145g1_resource_map(); |
| 126 | //setup_default_resource_map(); |
| 127 | |
Oskar Enoksson | df073cb | 2011-10-04 22:15:51 +0200 | [diff] [blame] | 128 | setup_coherent_ht_domain(); |
| 129 | wait_all_core0_started(); |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 130 | #if CONFIG_LOGICAL_CPUS |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 131 | // It is said that we should start core1 after all core0 launched |
| 132 | start_other_cores(); |
| 133 | wait_all_other_cores_started(bsp_apicid); |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 134 | #endif |
| 135 | |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 136 | ht_setup_chains_x(sysinfo); |
Oskar Enoksson | aaedeca | 2014-02-11 22:51:03 +0100 | [diff] [blame] | 137 | #if CONFIG_SET_FIDVID |
| 138 | /* Check to see if processor is capable of changing FIDVID */ |
| 139 | /* otherwise it will throw a GP# when reading FIDVID_STATUS */ |
| 140 | struct cpuid_result cpuid1 = cpuid(0x80000007); |
| 141 | if ((cpuid1.edx & 0x6) == 0x6) { |
| 142 | { |
| 143 | /* Read FIDVID_STATUS */ |
| 144 | msr_t msr; |
| 145 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 146 | printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
Oskar Enoksson | aaedeca | 2014-02-11 22:51:03 +0100 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | enable_fid_change(); |
| 150 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 151 | init_fidvid_bsp(bsp_apicid); |
| 152 | |
| 153 | // show final fid and vid |
| 154 | { |
| 155 | msr_t msr; |
| 156 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 157 | printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
Oskar Enoksson | aaedeca | 2014-02-11 22:51:03 +0100 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | } else { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 161 | printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); |
Oskar Enoksson | aaedeca | 2014-02-11 22:51:03 +0100 | [diff] [blame] | 162 | } |
| 163 | #endif |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 164 | |
Oskar Enoksson | df073cb | 2011-10-04 22:15:51 +0200 | [diff] [blame] | 165 | needs_reset |= optimize_link_coherent_ht(); |
| 166 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 167 | |
| 168 | if (needs_reset) { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 169 | printk(BIOS_INFO, "ht reset -\n"); |
Oskar Enoksson | df073cb | 2011-10-04 22:15:51 +0200 | [diff] [blame] | 170 | soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); |
| 171 | } |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 172 | |
| 173 | enable_smbus(); |
| 174 | |
| 175 | int i; |
| 176 | for(i=0;i<2;i++) { |
Oskar Enoksson | df073cb | 2011-10-04 22:15:51 +0200 | [diff] [blame] | 177 | activate_spd_rom(&sysinfo->ctrl[i]); |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 178 | } |
Oskar Enoksson | df073cb | 2011-10-04 22:15:51 +0200 | [diff] [blame] | 179 | for(i=RC0;i<=RC1;i<<=1) { |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 180 | change_i2c_mux(i); |
| 181 | } |
| 182 | |
Oskar Enoksson | df073cb | 2011-10-04 22:15:51 +0200 | [diff] [blame] | 183 | //dump_spd_registers(&sysinfo->ctrl[0]); |
| 184 | //dump_spd_registers(&sysinfo->ctrl[1]); |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 185 | //dump_smbus_registers(); |
| 186 | |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 187 | allow_all_aps_stop(bsp_apicid); |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 188 | |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 189 | //It's the time to set ctrl now; |
| 190 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 191 | |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 192 | memreset_setup(); |
Oskar Enoksson | aaedeca | 2014-02-11 22:51:03 +0100 | [diff] [blame] | 193 | #if CONFIG_SET_FIDVID |
| 194 | init_timer(); // Need to use TMICT to synchronize FID/VID |
| 195 | #endif |
Oskar Enoksson | f5e102d | 2011-11-07 18:31:33 +0100 | [diff] [blame] | 196 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
Oskar Enoksson | 37106a7 | 2010-08-20 20:37:27 +0000 | [diff] [blame] | 197 | |
| 198 | //dump_pci_devices(); |
| 199 | |
| 200 | post_cache_as_ram(); |
| 201 | } |