Oskar Enoksson | 2516f2e | 2014-02-08 00:17:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com> |
| 5 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> |
| 6 | * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Oskar Enoksson | 2516f2e | 2014-02-08 00:17:21 +0100 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | /* |
| 19 | * ISA portions taken from QEMU acpi-dsdt.dsl. |
| 20 | */ |
| 21 | |
| 22 | DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) |
| 23 | { |
| 24 | // Name (SPIO, 0x2E) // SuperIO (w83627hf) |
| 25 | Name (SPI2, 0x4E) // Unknown National Semiconductors (EPM3128A?) |
| 26 | Name (IO1B, 0x0680) // GPIO Base (?) |
| 27 | Name (IO1L, 0x80) |
| 28 | //Name (IO2B, 0x0295) // Hardware monitor |
| 29 | //Name (IO2L, 0x02) |
| 30 | Name (PMBS, 0x2000) // Power Management Base |
| 31 | Name (PMLN, 0xC0) // Power Management Length |
| 32 | Name (GPBS, 0x20C0) |
| 33 | Name (GPLN, 0x20) |
| 34 | Name (SMBS, 0x20E0) |
| 35 | Name (SMBL, 0x20) |
| 36 | |
| 37 | #define NO_W83627HF_FDC // don't expose the floppy disk controller |
| 38 | #define NO_W83627HF_FDC_ENUM // don't try to enumerate the connected floppy drives |
| 39 | #define NO_W83627HF_PPORT // don't expose the parallel port |
| 40 | //#define NO_W83627HF_UARTA // don't expose the first serial port |
| 41 | #define NO_W83627HF_UARTB // don't expose the second serial port (already hidden |
| 42 | // if UARTB is configured as IRDA port by firmware) |
| 43 | #define NO_W83627HF_IRDA // don't expose the IRDA port (already hidden if UARTB is |
| 44 | // configured as serial port by firmware) |
| 45 | #define NO_W83627HF_CIR // don't expose the Consumer Infrared functionality |
| 46 | //#define NO_W83627HF_KBC // don't expose the keyboard controller |
| 47 | //#define NO_W83627HF_PS2M // don't expose the PS/2 mouse functionality of the |
| 48 | // keyboard controller |
| 49 | #define NO_W83627HF_GAME // don't expose the game port |
| 50 | #define NO_W83627HF_MIDI // don't expose the MIDI port |
| 51 | // #define NO_W83627HF_HWMON // don't expose the hardware monitor as |
| 52 | // PnP "Motherboard Resource" |
| 53 | // Scope (\_PR) and relevant CPU? objects are auto-generated in SSDT |
| 54 | |
| 55 | Scope (\_SB) { // Root of the bus hierarchy |
| 56 | Device (PCI0) { // Top PCI device (AMD K8 Northbridge 1) |
| 57 | |
| 58 | Device(MBRS) { |
| 59 | Name (_HID, EisaId ("PNP0C02")) |
| 60 | Name (_UID, 0x01) |
| 61 | External(_CRS) /* Resource Template in SSDT */ |
| 62 | } |
| 63 | |
| 64 | // The following symbols are assumed to be created by coreboot |
| 65 | External (BUSN) |
| 66 | External (PCIO) |
| 67 | External (MMIO) |
| 68 | External (SBLK) |
| 69 | External (CBST) |
| 70 | External (SBDN) |
| 71 | External (TOM1) // Top Of Memory 1 (low 4GB ?) |
| 72 | External (HCLK) // Hypertransport possible CLocK frequencies |
| 73 | External (HCDN) // Hypertransport Controller Device Numbers |
| 74 | |
| 75 | Name (_HID, EisaId ("PNP0A03")) |
| 76 | Name (_ADR, 0x00180000) |
| 77 | //Name (_UID, 0x00) |
| 78 | Name (_UID, 0x01) |
| 79 | |
| 80 | Name (HCIN, 0x00) // HC1 |
| 81 | Method (_BBN, 0, NotSerialized) { |
| 82 | Return (GBUS (GHCN(HCIN), GHCL(HCIN))) |
| 83 | } |
| 84 | Method (_CRS, 0, Serialized) { |
| 85 | Name (BUF0, ResourceTemplate () { |
| 86 | // PCI Configuration address space address/data |
| 87 | IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) |
| 88 | IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h |
| 89 | IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h |
| 90 | WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 91 | 0x0000, // Address Space Granularity |
| 92 | 0x8100, // Address Range Minimum |
| 93 | 0xFFFF, // Address Range Maximum |
| 94 | 0x0000, // Address Translation Offset |
| 95 | 0x7F00,,, |
| 96 | , TypeStatic) //8100h-FFFFh |
| 97 | DWordMemory (ResourceProducer, PosDecode, |
| 98 | MinFixed, MaxFixed, Cacheable, ReadWrite, |
| 99 | 0x00000000, // Address Space Granularity |
| 100 | 0x000C0000, // Address Range Minimum |
| 101 | 0x000CFFFF, // Address Range Maximum |
| 102 | 0x00000000, // Address Translation Offset |
| 103 | 0x00010000,,, |
| 104 | , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh |
| 105 | Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF |
| 106 | WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 107 | 0x0000, // Address Space Granularity |
| 108 | 0x0000, // Address Range Minimum |
| 109 | 0x03AF, // Address Range Maximum |
| 110 | 0x0000, // Address Translation Offset |
| 111 | 0x03B0,,, |
| 112 | , TypeStatic) //0-CF7h |
| 113 | WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 114 | 0x0000, // Address Space Granularity |
| 115 | 0x03E0, // Address Range Minimum |
| 116 | 0x0CF7, // Address Range Maximum |
| 117 | 0x0000, // Address Translation Offset |
| 118 | 0x0918,,, |
| 119 | , TypeStatic) //0-CF7h |
| 120 | }) |
Edward O'Callaghan | f7d8f09 | 2014-05-31 13:57:52 +1000 | [diff] [blame] | 121 | \_SB.OSVR () |
Oskar Enoksson | 2516f2e | 2014-02-08 00:17:21 +0100 | [diff] [blame] | 122 | CreateDWordField (BUF0, 0x3E, VLEN) |
| 123 | CreateDWordField (BUF0, 0x36, VMAX) |
| 124 | CreateDWordField (BUF0, 0x32, VMIN) |
| 125 | ShiftLeft (VGA1, 0x09, Local0) |
| 126 | Add (VMIN, Local0, VMAX) |
| 127 | Decrement (VMAX) |
| 128 | Store (Local0, VLEN) |
| 129 | Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) |
| 130 | Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) |
| 131 | Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) |
| 132 | Return (Local3) |
| 133 | } |
| 134 | #include "acpi/pci0_hc.asl" |
| 135 | } |
| 136 | Device (PCI1) { |
| 137 | Name (_HID, "PNP0A03") |
| 138 | Name (_ADR, 0x00190000) |
| 139 | Name (_UID, 0x02) |
| 140 | Method (_STA, 0, NotSerialized) { |
| 141 | Return (\_SB.PCI0.CBST) |
| 142 | } |
| 143 | //Name (HCIN, 0x01) // HC2 |
| 144 | //Method (_BBN, 0, NotSerialized) { |
| 145 | // Return (GBUS (GHCN(HCIN), GHCL(HCIN))) |
| 146 | //} |
| 147 | Name (_BBN, 0x00) |
| 148 | } |
| 149 | Device (PWRB) { |
| 150 | Name (_HID, EisaId ("PNP0C0C")) |
| 151 | Name (_UID, 0xAA) |
| 152 | Name (_STA, 0x0B) |
| 153 | } |
| 154 | } |
| 155 | Scope (_GPE) { |
| 156 | Method (_L08, 0, NotSerialized) { |
| 157 | Notify (\_SB.PCI0, 0x02) //PME# Wakeup |
| 158 | Notify (\_SB.PCI0.TP2P.ETHR, 0x02) |
| 159 | Notify (\_SB.PWRB, 0x02) |
| 160 | } |
| 161 | Method (_L0F, 0, NotSerialized) { |
| 162 | Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup |
| 163 | Notify (\_SB.PCI0.TP2P.USB1, 0x02) |
| 164 | Notify (\_SB.PWRB, 0x02) |
| 165 | } |
| 166 | Method (_L22, 0, NotSerialized) { // GPIO18 (LID) - Pogo 0 Bridge B |
| 167 | Notify (\_SB.PCI0.PG0B, 0x02) |
| 168 | Notify (\_SB.PWRB, 0x02) |
| 169 | } |
| 170 | Method (_L29, 0, NotSerialized) { // GPIO25 (Suspend) - Pogo 0 Bridge A |
| 171 | Notify (\_SB.PCI0.PG0A, 0x02) |
| 172 | Notify (\_SB.PWRB, 0x02) |
| 173 | } |
| 174 | } |
| 175 | OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS ram (?) |
| 176 | Field (KSB0, ByteAcc, NoLock, Preserve) { |
| 177 | KSBI, 8, // Index |
| 178 | KSBD, 8 // Data |
| 179 | } |
| 180 | /* |
| 181 | OperationRegion (IHHM, SystemIO, IO2B, IO2L) // Hardware monitor |
| 182 | Field (IHHM, ByteAcc, NoLock, Preserve) { |
| 183 | HHMI, 8, // Index |
| 184 | HHMD, 8 // Data |
| 185 | } |
| 186 | */ |
| 187 | // Method (_BFS, 1, NotSerialized) { |
| 188 | // Control method executed immediately following a wake event. |
| 189 | // Arg0 => Value of the sleeping state from which woken (1=S1, 2=S2 ...) |
| 190 | // Optional |
| 191 | //} |
| 192 | |
| 193 | Method (_PTS, 1, NotSerialized) { |
| 194 | // Control method used to Prepare To Sleep. |
| 195 | // Arg0 => Value of the sleeping state (1=S1, 2=S2 ...) |
| 196 | Or (Arg0, 0xF0, Local0) |
| 197 | Store (Local0, DBG8) |
| 198 | } |
| 199 | |
| 200 | // Method (_GTS, 1, NotSerialized) { |
| 201 | // Control method executed just prior to setting the sleep enable (SLP_EN) bit. |
| 202 | // Arg0 => Value of the sleeping state (1=S1, 2=S2 ...) |
| 203 | // Optional |
| 204 | //} |
| 205 | |
| 206 | // System \_Sx states |
| 207 | // Four bytes must be stored for each supported power state: |
| 208 | // 0:7 Value for PM1a_CNT.SLP_TYP register to enter this system state. |
| 209 | // 8:f Value for PM1b_CNT.SLP_TYP register to enter this system state. |
| 210 | // To enter any given state, OSPM must write the PM1a_CNT.SLP_TYP |
| 211 | // register before the PM1b_CNT.SLP_TYP register. |
| 212 | // 10:1f Reserved |
| 213 | // The states are: |
| 214 | // S0 : Working |
| 215 | // S1 : Sleeping with Processor Context maintained |
| 216 | // S2 : Sleeping with Processor Context not maintained |
| 217 | // S3 : Same as S2, but more power saving (e.g. suspend to RAM) |
| 218 | // S4 : DRAM context not maintained (e.g. suspend to disk) |
| 219 | // S5 : Soft Off |
| 220 | // If only S0 and S5 are declared then no wake-up methods are needed |
| 221 | Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) |
| 222 | // S1 support should work, but never wakes up, so it's commented out |
| 223 | //Name (\_S1, Package () { 0x01, 0x01, 0x01, 0x01 }) |
| 224 | //Name (\_S3, Package () { 0x05, 0x05, 0x05, 0x05 }) |
| 225 | Name (\_S5, Package () { 0x07, 0x07, 0x07, 0x07 }) |
| 226 | //Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) |
| 227 | |
| 228 | Method (WAK, 1, NotSerialized) {} |
| 229 | |
| 230 | Name (WAKP, Package (0x02) { 0x00, 0x00 }) |
| 231 | // Status |
| 232 | // 0: 0 Wake was signaled but failed due to lack of power. |
| 233 | // 1: 1 Wake was signaled but failed due to thermal condition |
| 234 | // 2:31 Reserved |
| 235 | // PSS |
| 236 | // 0:1f If non-zero, the effective S-state the power supply really entered. |
| 237 | |
| 238 | Method (_WAK, 1, NotSerialized) { |
| 239 | // System Wake |
| 240 | // Arg0: The value of the sleeping state from which woken (1=S1, ...) |
| 241 | // Result: (2 DWORD package) |
| 242 | ShiftLeft (Arg0, 0x04, DBG8) |
| 243 | WAK (Arg0) |
| 244 | Store (0xFF, KSBI) // Clear 0xFF in CMOS RAM |
| 245 | Store (0x00, KSBD) |
| 246 | If (LEqual (Arg0, 0x01)) { // Wake from S1 state |
| 247 | And (\_SB.PCI0.GSTS, 0x10, Local0) |
| 248 | And (Local0, \_SB.PCI0.GNBL, Local0) |
| 249 | If (Local0) { |
| 250 | Notify (\_SB.PWRB, 0x02) |
| 251 | } |
| 252 | } |
| 253 | Store (\_SB.PCI0.GSTS, \_SB.PCI0.GSTS) |
| 254 | Store (\_SB.PCI0.STMC, \_SB.PCI0.STMC) |
| 255 | Store (\_SB.PCI0.STC0, \_SB.PCI0.STC0) |
| 256 | Store (\_SB.PCI0.STC1, \_SB.PCI0.STC1) |
| 257 | Store (\_SB.PCI0.STHW, \_SB.PCI0.STHW) |
| 258 | If (LEqual (Arg0, 0x03)) { // Wake from S3 state |
| 259 | Notify (\_SB.PCI0.TP2P.USB0, 0x01) |
| 260 | } |
| 261 | Store (0xC0, \_SB.PCI0.SWSM) |
| 262 | If (DerefOf (Index (WAKP, 0x00))) { |
| 263 | Store (0x00, Index (WAKP, 0x01)) |
| 264 | } Else { |
| 265 | Store (Arg0, Index (WAKP, 0x01)) |
| 266 | } |
| 267 | Return (WAKP) |
| 268 | } |
| 269 | |
| 270 | Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode |
| 271 | Method (_PIC, 1, NotSerialized) { //PIC Flag and Interface Method |
| 272 | // Control method that conveys interrupt model in use to the system |
| 273 | // firmware. OS reports interrupt model in use. |
| 274 | // 0 => PIC Mode |
| 275 | // 1 => APIC Mode |
| 276 | // 2 => SAPIC Mode |
| 277 | // 3.. => Reserved |
| 278 | Store (Arg0, PICF) |
| 279 | } |
| 280 | OperationRegion (DEB8, SystemIO, 0x80, 0x01) |
| 281 | Field (DEB8, ByteAcc, Lock, Preserve) { |
| 282 | DBG8, 8 |
| 283 | } |
| 284 | OperationRegion (DEB9, SystemIO, 0x90, 0x01) |
| 285 | Field (DEB9, ByteAcc, Lock, Preserve) { |
| 286 | DBG9, 8 |
| 287 | } |
| 288 | OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) |
| 289 | Field (EXTM, WordAcc, Lock, Preserve) { |
| 290 | AMEM, 32 |
| 291 | } |
| 292 | OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) |
| 293 | Field (VGAM, ByteAcc, Lock, Preserve) { |
| 294 | VGA1, 8 // Video memory length (in 2k units?) |
| 295 | } |
| 296 | OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) |
| 297 | Field (GRAM, ByteAcc, Lock, Preserve) { |
| 298 | Offset (0x10), |
| 299 | FLG0, 8 |
| 300 | } |
| 301 | OperationRegion (Z007, SystemIO, 0x21, 0x01) |
| 302 | Field (Z007, ByteAcc, NoLock, Preserve) { |
| 303 | Z008, 8 |
| 304 | } |
| 305 | OperationRegion (Z009, SystemIO, 0xA1, 0x01) |
| 306 | Field (Z009, ByteAcc, NoLock, Preserve) { |
| 307 | Z00A, 8 |
| 308 | } |
| 309 | #include "northbridge/amd/amdk8/util.asl" |
| 310 | } |