blob: 92673031f907cb6a9583c82f15416ef942af69a8 [file] [log] [blame]
jinkun.hong692a2c02015-01-07 08:57:48 +08001##
2## This file is part of the coreboot project.
3##
4## Copyright 2014 Rockchip Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
jinkun.hong692a2c02015-01-07 08:57:48 +080015
16if BOARD_GOOGLE_VEYRON_RIALTO
17
18config BOARD_SPECIFIC_OPTIONS # dummy
19 def_bool y
Stefan Reinauer82c706e2015-03-30 12:20:55 -070020 select BOARD_ID_AUTO
jinkun.hong692a2c02015-01-07 08:57:48 +080021 select BOARD_ROMSIZE_KB_4096
jinkun.hong692a2c02015-01-07 08:57:48 +080022 select COMMON_CBFS_SPI_WRAPPER
23 select HAVE_HARD_RESET
Martin Rothc0c115b2015-08-21 14:37:02 -060024 select MAINBOARD_HAS_NATIVE_VGA_INIT
jinkun.hong692a2c02015-01-07 08:57:48 +080025 select MAINBOARD_DO_NATIVE_VGA_INIT
26 select MAINBOARD_HAS_CHROMEOS
jinkun.hong692a2c02015-01-07 08:57:48 +080027 select RAM_CODE_SUPPORT
jinkun.hong692a2c02015-01-07 08:57:48 +080028 select SOC_ROCKCHIP_RK3288
29 select SPI_FLASH
30 select SPI_FLASH_GIGADEVICE
31 select SPI_FLASH_WINBOND
jinkun.hong692a2c02015-01-07 08:57:48 +080032
Martin Roth967cd9a2015-08-18 14:22:58 -060033config CHROMEOS
34 select CHROMEOS_VBNV_FLASH
35 select PHYSICAL_REC_SWITCH
Martin Roth8c12d6e2015-08-24 15:55:29 -060036 select VIRTUAL_DEV_SWITCH
Martin Roth967cd9a2015-08-18 14:22:58 -060037
jinkun.hong692a2c02015-01-07 08:57:48 +080038config MAINBOARD_DIR
39 string
40 default google/veyron_rialto
41
42config MAINBOARD_PART_NUMBER
43 string
44 default "Veyron_Rialto"
45
46config MAINBOARD_VENDOR
47 string
48 default "Google"
49
jinkun.hong692a2c02015-01-07 08:57:48 +080050config BOOT_MEDIA_SPI_BUS
Martin Roth595e7772015-04-26 18:53:26 -060051 int
52 default 2
jinkun.hong692a2c02015-01-07 08:57:48 +080053
jinkun.hong692a2c02015-01-07 08:57:48 +080054config DRIVER_TPM_I2C_BUS
55 hex
56 default 0x1
57
58config DRIVER_TPM_I2C_ADDR
59 hex
60 default 0x20
61
62config CONSOLE_SERIAL_UART_ADDRESS
63 hex
Patrick Georgi01368ed2015-04-16 15:27:52 +020064 depends on DRIVERS_UART
jinkun.hong692a2c02015-01-07 08:57:48 +080065 default 0xFF690000
66
jinkun.hong692a2c02015-01-07 08:57:48 +080067config PMIC_BUS
68 int
69 default 0
70
71endif # BOARD_GOOGLE_VEYRON_RIALTO