blob: d0456d7cc40d53ba2d0994e6432357feb90f2ec7 [file] [log] [blame]
David Hendricks113ef812015-05-13 13:58:24 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
David Hendricks113ef812015-05-13 13:58:24 -070014 */
15
16#include <boardid.h>
17#include <console/console.h>
18#include <gpio.h>
19#include <stdlib.h>
20
21uint8_t board_id(void)
22{
23 static int id = -1;
24 static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
25 [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
26
27 if (id < 0) {
28 id = gpio_base2_value(pins, ARRAY_SIZE(pins));
29 printk(BIOS_SPEW, "Board ID: %d.\n", id);
30 }
31
32 return id;
33}
34
35uint32_t ram_code(void)
36{
37 uint32_t code;
38 static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
39 [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
40
41 code = gpio_base2_value(pins, ARRAY_SIZE(pins));
42 printk(BIOS_SPEW, "RAM Config: %u.\n", code);
43
44 return code;
45}