Katie Roberts-Hoffman | b262c72 | 2014-10-23 19:14:30 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Katie Roberts-Hoffman | b262c72 | 2014-10-23 19:14:30 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <arch/cache.h> |
| 17 | #include <arch/exception.h> |
| 18 | #include <arch/stages.h> |
| 19 | #include <armv7.h> |
| 20 | #include <assert.h> |
| 21 | #include <cbfs.h> |
| 22 | #include <cbmem.h> |
| 23 | #include <console/console.h> |
| 24 | #include <delay.h> |
| 25 | #include <program_loading.h> |
| 26 | #include <soc/sdram.h> |
| 27 | #include <soc/clock.h> |
| 28 | #include <soc/pwm.h> |
| 29 | #include <soc/grf.h> |
Julius Werner | dbfa9d5 | 2014-12-05 17:29:42 -0800 | [diff] [blame] | 30 | #include <soc/rk808.h> |
Katie Roberts-Hoffman | b262c72 | 2014-10-23 19:14:30 -0700 | [diff] [blame] | 31 | #include <soc/tsadc.h> |
| 32 | #include <stdlib.h> |
| 33 | #include <symbols.h> |
| 34 | #include <timestamp.h> |
| 35 | #include <types.h> |
| 36 | #include <vendorcode/google/chromeos/chromeos.h> |
| 37 | |
Julius Werner | dbfa9d5 | 2014-12-05 17:29:42 -0800 | [diff] [blame] | 38 | #include "board.h" |
Katie Roberts-Hoffman | b262c72 | 2014-10-23 19:14:30 -0700 | [diff] [blame] | 39 | |
| 40 | static void regulate_vdd_log(unsigned int mv) |
| 41 | { |
| 42 | unsigned int duty_ns; |
| 43 | const u32 period_ns = 2000; /* pwm period: 2000ns */ |
| 44 | const u32 max_regulator_mv = 1350; /* 1.35V */ |
| 45 | const u32 min_regulator_mv = 870; /* 0.87V */ |
| 46 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 47 | write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1); |
Katie Roberts-Hoffman | b262c72 | 2014-10-23 19:14:30 -0700 | [diff] [blame] | 48 | |
| 49 | assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv)); |
| 50 | |
| 51 | duty_ns = (max_regulator_mv - mv) * period_ns / |
| 52 | (max_regulator_mv - min_regulator_mv); |
| 53 | |
| 54 | pwm_init(1, period_ns, duty_ns); |
| 55 | } |
| 56 | |
| 57 | static void configure_l2ctlr(void) |
| 58 | { |
| 59 | uint32_t l2ctlr; |
| 60 | |
| 61 | l2ctlr = read_l2ctlr(); |
| 62 | l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ |
| 63 | |
| 64 | /* |
| 65 | * Data RAM write latency: 2 cycles |
| 66 | * Data RAM read latency: 2 cycles |
| 67 | * Data RAM setup latency: 1 cycle |
| 68 | * Tag RAM write latency: 1 cycle |
| 69 | * Tag RAM read latency: 1 cycle |
| 70 | * Tag RAM setup latency: 1 cycle |
| 71 | */ |
| 72 | l2ctlr |= (1 << 3 | 1 << 0); |
| 73 | write_l2ctlr(l2ctlr); |
| 74 | } |
| 75 | |
Julius Werner | dbfa9d5 | 2014-12-05 17:29:42 -0800 | [diff] [blame] | 76 | static void sdmmc_power_off(void) |
| 77 | { |
David Hendricks | 4d24421 | 2015-01-12 13:13:30 -0800 | [diff] [blame] | 78 | rk808_configure_ldo(4, 0); /* VCCIO_SD */ |
| 79 | rk808_configure_ldo(5, 0); /* VCC33_SD */ |
Julius Werner | dbfa9d5 | 2014-12-05 17:29:42 -0800 | [diff] [blame] | 80 | } |
| 81 | |
Katie Roberts-Hoffman | b262c72 | 2014-10-23 19:14:30 -0700 | [diff] [blame] | 82 | void main(void) |
| 83 | { |
Furquan Shaikh | d17a862 | 2014-11-03 14:39:11 -0800 | [diff] [blame] | 84 | timestamp_add_now(TS_START_ROMSTAGE); |
Katie Roberts-Hoffman | b262c72 | 2014-10-23 19:14:30 -0700 | [diff] [blame] | 85 | |
| 86 | console_init(); |
| 87 | configure_l2ctlr(); |
| 88 | tsadc_init(); |
| 89 | |
Julius Werner | dbfa9d5 | 2014-12-05 17:29:42 -0800 | [diff] [blame] | 90 | /* Need to power cycle SD card to ensure it is properly reset. */ |
| 91 | sdmmc_power_off(); |
| 92 | |
Katie Roberts-Hoffman | b262c72 | 2014-10-23 19:14:30 -0700 | [diff] [blame] | 93 | /* vdd_log 1200mv is enough for ddr run 666Mhz */ |
| 94 | regulate_vdd_log(1200); |
Furquan Shaikh | d17a862 | 2014-11-03 14:39:11 -0800 | [diff] [blame] | 95 | |
| 96 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 97 | |
Katie Roberts-Hoffman | b262c72 | 2014-10-23 19:14:30 -0700 | [diff] [blame] | 98 | sdram_init(get_sdram_config()); |
Furquan Shaikh | d17a862 | 2014-11-03 14:39:11 -0800 | [diff] [blame] | 99 | |
| 100 | timestamp_add_now(TS_AFTER_INITRAM); |
Katie Roberts-Hoffman | b262c72 | 2014-10-23 19:14:30 -0700 | [diff] [blame] | 101 | |
| 102 | /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ |
| 103 | mmu_config_range((uintptr_t)_dram/MiB, |
huang lin | ee28c86 | 2015-01-26 21:04:55 +0800 | [diff] [blame] | 104 | sdram_size_mb(), DCACHE_WRITEBACK); |
Katie Roberts-Hoffman | b262c72 | 2014-10-23 19:14:30 -0700 | [diff] [blame] | 105 | mmu_config_range((uintptr_t)_dma_coherent/MiB, |
| 106 | _dma_coherent_size/MiB, DCACHE_OFF); |
| 107 | |
| 108 | cbmem_initialize_empty(); |
| 109 | |
Katie Roberts-Hoffman | b262c72 | 2014-10-23 19:14:30 -0700 | [diff] [blame] | 110 | run_ramstage(); |
| 111 | } |